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1; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
2
3define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
4;CHECK: vpadals8:
5;CHECK: vpadal.s8
6	%tmp1 = load <4 x i16>* %A
7	%tmp2 = load <8 x i8>* %B
8	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
9	ret <4 x i16> %tmp3
10}
11
12define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
13;CHECK: vpadals16:
14;CHECK: vpadal.s16
15	%tmp1 = load <2 x i32>* %A
16	%tmp2 = load <4 x i16>* %B
17	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
18	ret <2 x i32> %tmp3
19}
20
21define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
22;CHECK: vpadals32:
23;CHECK: vpadal.s32
24	%tmp1 = load <1 x i64>* %A
25	%tmp2 = load <2 x i32>* %B
26	%tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
27	ret <1 x i64> %tmp3
28}
29
30define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
31;CHECK: vpadalu8:
32;CHECK: vpadal.u8
33	%tmp1 = load <4 x i16>* %A
34	%tmp2 = load <8 x i8>* %B
35	%tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2)
36	ret <4 x i16> %tmp3
37}
38
39define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
40;CHECK: vpadalu16:
41;CHECK: vpadal.u16
42	%tmp1 = load <2 x i32>* %A
43	%tmp2 = load <4 x i16>* %B
44	%tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2)
45	ret <2 x i32> %tmp3
46}
47
48define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
49;CHECK: vpadalu32:
50;CHECK: vpadal.u32
51	%tmp1 = load <1 x i64>* %A
52	%tmp2 = load <2 x i32>* %B
53	%tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2)
54	ret <1 x i64> %tmp3
55}
56
57define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
58;CHECK: vpadalQs8:
59;CHECK: vpadal.s8
60	%tmp1 = load <8 x i16>* %A
61	%tmp2 = load <16 x i8>* %B
62	%tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
63	ret <8 x i16> %tmp3
64}
65
66define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
67;CHECK: vpadalQs16:
68;CHECK: vpadal.s16
69	%tmp1 = load <4 x i32>* %A
70	%tmp2 = load <8 x i16>* %B
71	%tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
72	ret <4 x i32> %tmp3
73}
74
75define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
76;CHECK: vpadalQs32:
77;CHECK: vpadal.s32
78	%tmp1 = load <2 x i64>* %A
79	%tmp2 = load <4 x i32>* %B
80	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
81	ret <2 x i64> %tmp3
82}
83
84define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
85;CHECK: vpadalQu8:
86;CHECK: vpadal.u8
87	%tmp1 = load <8 x i16>* %A
88	%tmp2 = load <16 x i8>* %B
89	%tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2)
90	ret <8 x i16> %tmp3
91}
92
93define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
94;CHECK: vpadalQu16:
95;CHECK: vpadal.u16
96	%tmp1 = load <4 x i32>* %A
97	%tmp2 = load <8 x i16>* %B
98	%tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2)
99	ret <4 x i32> %tmp3
100}
101
102define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
103;CHECK: vpadalQu32:
104;CHECK: vpadal.u32
105	%tmp1 = load <2 x i64>* %A
106	%tmp2 = load <4 x i32>* %B
107	%tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2)
108	ret <2 x i64> %tmp3
109}
110
111declare <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
112declare <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
113declare <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
114
115declare <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16>, <8 x i8>) nounwind readnone
116declare <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32>, <4 x i16>) nounwind readnone
117declare <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64>, <2 x i32>) nounwind readnone
118
119declare <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
120declare <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
121declare <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
122
123declare <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16>, <16 x i8>) nounwind readnone
124declare <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32>, <8 x i16>) nounwind readnone
125declare <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64>, <4 x i32>) nounwind readnone
126