1; RUN: llc < %s -march=cellspu | FileCheck %s 2 3; ModuleID = 'loads.bc' 4target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" 5target triple = "spu" 6 7define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly { 8entry: 9 %tmp1 = load <4 x float>* %a 10 ret <4 x float> %tmp1 11; CHECK: lqd $3, 0($3) 12} 13 14define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly { 15entry: 16 %arrayidx = getelementptr <4 x float>* %a, i32 1 17 %tmp1 = load <4 x float>* %arrayidx 18 ret <4 x float> %tmp1 19; CHECK: lqd $3, 16($3) 20} 21 22 23declare <4 x i32>* @getv4f32ptr() 24define <4 x i32> @func() { 25 ;CHECK: brasl 26 ; we need to have some instruction to move the result to safety. 27 ; which instruction (lr, stqd...) depends on the regalloc 28 ;CHECK: {{.*}} 29 ;CHECK: brasl 30 %rv1 = call <4 x i32>* @getv4f32ptr() 31 %rv2 = call <4 x i32>* @getv4f32ptr() 32 %rv3 = load <4 x i32>* %rv1 33 ret <4 x i32> %rv3 34} 35 36define <4 x float> @load_undef(){ 37 ; CHECK: lqd $3, 0($3) 38 %val = load <4 x float>* undef 39 ret <4 x float> %val 40} 41 42;check that 'misaligned' loads that may span two memory chunks 43;have two loads. Don't check for the bitmanipulation, as that 44;might change with improved algorithms or scheduling 45define i32 @load_misaligned( i32* %ptr ){ 46;CHECK: load_misaligned 47;CHECK: lqd 48;CHECK: lqd 49;CHECK: bi $lr 50 %rv = load i32* %ptr, align 2 51 ret i32 %rv 52} 53 54define <4 x i32> @load_null_vec( ) { 55;CHECK: lqa 56;CHECK: bi $lr 57 %rv = load <4 x i32>* null 58 ret <4 x i32> %rv 59} 60