1; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s 2target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" 3 4define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone { 5entry: 6; CHECK: test1: 7; CHECK: btl 8; CHECK-NEXT: movl $12, %eax 9; CHECK-NEXT: cmovael (%rcx), %eax 10; CHECK-NEXT: ret 11 12 %0 = lshr i32 %x, %n ; <i32> [#uses=1] 13 %1 = and i32 %0, 1 ; <i32> [#uses=1] 14 %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1] 15 %v = load i32* %vp 16 %.0 = select i1 %toBool, i32 %v, i32 12 ; <i32> [#uses=1] 17 ret i32 %.0 18} 19define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone { 20entry: 21; CHECK: test2: 22; CHECK: btl 23; CHECK-NEXT: movl $12, %eax 24; CHECK-NEXT: cmovbl (%rcx), %eax 25; CHECK-NEXT: ret 26 27 %0 = lshr i32 %x, %n ; <i32> [#uses=1] 28 %1 = and i32 %0, 1 ; <i32> [#uses=1] 29 %toBool = icmp eq i32 %1, 0 ; <i1> [#uses=1] 30 %v = load i32* %vp 31 %.0 = select i1 %toBool, i32 12, i32 %v ; <i32> [#uses=1] 32 ret i32 %.0 33} 34 35 36; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination 37; if the condition is false. An explicit zero-extend (movl) is needed 38; after the cmov. 39 40declare void @bar(i64) nounwind 41 42define void @test3(i64 %a, i64 %b, i1 %p) nounwind { 43; CHECK: test3: 44; CHECK: cmovnel %edi, %esi 45; CHECK-NEXT: movl %esi, %edi 46 47 %c = trunc i64 %a to i32 48 %d = trunc i64 %b to i32 49 %e = select i1 %p, i32 %c, i32 %d 50 %f = zext i32 %e to i64 51 call void @bar(i64 %f) 52 ret void 53} 54 55 56 57; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional 58; move without recomputing EFLAGS, because the expansion of the conditional 59; move with control flow may clobber EFLAGS (e.g., with xor, to set the 60; register to zero). 61 62; The test is a little awkward; the important part is that there's a test before the 63; setne. 64; PR4814 65 66 67@g_3 = external global i8 ; <i8*> [#uses=1] 68@g_96 = external global i8 ; <i8*> [#uses=2] 69@g_100 = external global i8 ; <i8*> [#uses=2] 70@_2E_str = external constant [15 x i8], align 1 ; <[15 x i8]*> [#uses=1] 71 72define i32 @test4() nounwind { 73entry: 74 %0 = load i8* @g_3, align 1 ; <i8> [#uses=2] 75 %1 = sext i8 %0 to i32 ; <i32> [#uses=1] 76 %.lobit.i = lshr i8 %0, 7 ; <i8> [#uses=1] 77 %tmp.i = zext i8 %.lobit.i to i32 ; <i32> [#uses=1] 78 %tmp.not.i = xor i32 %tmp.i, 1 ; <i32> [#uses=1] 79 %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i ; <i32> [#uses=1] 80 %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8 ; <i8> [#uses=1] 81 %2 = icmp eq i8 %retval56.i.i, 0 ; <i1> [#uses=2] 82 %g_96.promoted.i = load i8* @g_96 ; <i8> [#uses=3] 83 %3 = icmp eq i8 %g_96.promoted.i, 0 ; <i1> [#uses=2] 84 br i1 %3, label %func_4.exit.i, label %bb.i.i.i 85 86bb.i.i.i: ; preds = %entry 87 %4 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0] 88 br label %func_4.exit.i 89 90; CHECK: test4: 91; CHECK: g_100 92; CHECK: testb 93; CHECK-NOT: xor 94; CHECK: setne 95; CHECK-NEXT: testb 96 97func_4.exit.i: ; preds = %bb.i.i.i, %entry 98 %.not.i = xor i1 %2, true ; <i1> [#uses=1] 99 %brmerge.i = or i1 %3, %.not.i ; <i1> [#uses=1] 100 %.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0 ; <i8> [#uses=1] 101 br i1 %brmerge.i, label %func_1.exit, label %bb.i.i 102 103bb.i.i: ; preds = %func_4.exit.i 104 %5 = volatile load i8* @g_100, align 1 ; <i8> [#uses=0] 105 br label %func_1.exit 106 107func_1.exit: ; preds = %bb.i.i, %func_4.exit.i 108 %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ] ; <i8> [#uses=2] 109 store i8 %g_96.tmp.0.i, i8* @g_96 110 %6 = zext i8 %g_96.tmp.0.i to i32 ; <i32> [#uses=1] 111 %7 = tail call i32 (i8*, ...)* @printf(i8* noalias getelementptr ([15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind ; <i32> [#uses=0] 112 ret i32 0 113} 114 115declare i32 @printf(i8* nocapture, ...) nounwind 116 117 118; Should compile to setcc | -2. 119; rdar://6668608 120define i32 @test5(i32* nocapture %P) nounwind readonly { 121entry: 122; CHECK: test5: 123; CHECK: setg %al 124; CHECK: movzbl %al, %eax 125; CHECK: orl $-2, %eax 126; CHECK: ret 127 128 %0 = load i32* %P, align 4 ; <i32> [#uses=1] 129 %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1] 130 %iftmp.0.0 = select i1 %1, i32 -1, i32 -2 ; <i32> [#uses=1] 131 ret i32 %iftmp.0.0 132} 133 134define i32 @test6(i32* nocapture %P) nounwind readonly { 135entry: 136; CHECK: test6: 137; CHECK: setl %al 138; CHECK: movzbl %al, %eax 139; CHECK: leal 4(%rax,%rax,8), %eax 140; CHECK: ret 141 %0 = load i32* %P, align 4 ; <i32> [#uses=1] 142 %1 = icmp sgt i32 %0, 41 ; <i1> [#uses=1] 143 %iftmp.0.0 = select i1 %1, i32 4, i32 13 ; <i32> [#uses=1] 144 ret i32 %iftmp.0.0 145} 146 147 148; Don't try to use a 16-bit conditional move to do an 8-bit select, 149; because it isn't worth it. Just use a branch instead. 150define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind { 151; CHECK: test7: 152; CHECK: testb $1, %dil 153; CHECK-NEXT: jne LBB 154 155 %d = select i1 %c, i8 %a, i8 %b 156 ret i8 %d 157} 158