1; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s 2 3declare void @bar(i32) 4declare void @car(i32) 5declare void @dar(i32) 6declare void @ear(i32) 7declare void @far(i32) 8declare i1 @qux() 9 10@GHJK = global i32 0 11@HABC = global i32 0 12 13; BranchFolding should tail-merge the stores since they all precede 14; direct branches to the same place. 15 16; CHECK: tail_merge_me: 17; CHECK-NOT: GHJK 18; CHECK: movl $0, GHJK(%rip) 19; CHECK-NEXT: movl $1, HABC(%rip) 20; CHECK-NOT: GHJK 21 22define void @tail_merge_me() nounwind { 23entry: 24 %a = call i1 @qux() 25 br i1 %a, label %A, label %next 26next: 27 %b = call i1 @qux() 28 br i1 %b, label %B, label %C 29 30A: 31 call void @bar(i32 0) 32 store i32 0, i32* @GHJK 33 br label %M 34 35B: 36 call void @car(i32 1) 37 store i32 0, i32* @GHJK 38 br label %M 39 40C: 41 call void @dar(i32 2) 42 store i32 0, i32* @GHJK 43 br label %M 44 45M: 46 store i32 1, i32* @HABC 47 %c = call i1 @qux() 48 br i1 %c, label %return, label %altret 49 50return: 51 call void @ear(i32 1000) 52 ret void 53altret: 54 call void @far(i32 1001) 55 ret void 56} 57 58declare i8* @choose(i8*, i8*) 59 60; BranchFolding should tail-duplicate the indirect jump to avoid 61; redundant branching. 62 63; CHECK: tail_duplicate_me: 64; CHECK: movl $0, GHJK(%rip) 65; CHECK-NEXT: jmpq *%r 66; CHECK: movl $0, GHJK(%rip) 67; CHECK-NEXT: jmpq *%r 68; CHECK: movl $0, GHJK(%rip) 69; CHECK-NEXT: jmpq *%r 70 71define void @tail_duplicate_me() nounwind { 72entry: 73 %a = call i1 @qux() 74 %c = call i8* @choose(i8* blockaddress(@tail_duplicate_me, %return), 75 i8* blockaddress(@tail_duplicate_me, %altret)) 76 br i1 %a, label %A, label %next 77next: 78 %b = call i1 @qux() 79 br i1 %b, label %B, label %C 80 81A: 82 call void @bar(i32 0) 83 store i32 0, i32* @GHJK 84 br label %M 85 86B: 87 call void @car(i32 1) 88 store i32 0, i32* @GHJK 89 br label %M 90 91C: 92 call void @dar(i32 2) 93 store i32 0, i32* @GHJK 94 br label %M 95 96M: 97 indirectbr i8* %c, [label %return, label %altret] 98 99return: 100 call void @ear(i32 1000) 101 ret void 102altret: 103 call void @far(i32 1001) 104 ret void 105} 106 107; BranchFolding shouldn't try to merge the tails of two blocks 108; with only a branch in common, regardless of the fallthrough situation. 109 110; CHECK: dont_merge_oddly: 111; CHECK-NOT: ret 112; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} 113; CHECK-NEXT: jbe .LBB2_3 114; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} 115; CHECK-NEXT: ja .LBB2_4 116; CHECK-NEXT: .LBB2_2: 117; CHECK-NEXT: movb $1, %al 118; CHECK-NEXT: ret 119; CHECK-NEXT: .LBB2_3: 120; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} 121; CHECK-NEXT: jbe .LBB2_2 122; CHECK-NEXT: .LBB2_4: 123; CHECK-NEXT: xorb %al, %al 124; CHECK-NEXT: ret 125 126define i1 @dont_merge_oddly(float* %result) nounwind { 127entry: 128 %tmp4 = getelementptr float* %result, i32 2 129 %tmp5 = load float* %tmp4, align 4 130 %tmp7 = getelementptr float* %result, i32 4 131 %tmp8 = load float* %tmp7, align 4 132 %tmp10 = getelementptr float* %result, i32 6 133 %tmp11 = load float* %tmp10, align 4 134 %tmp12 = fcmp olt float %tmp8, %tmp11 135 br i1 %tmp12, label %bb, label %bb21 136 137bb: 138 %tmp23469 = fcmp olt float %tmp5, %tmp8 139 br i1 %tmp23469, label %bb26, label %bb30 140 141bb21: 142 %tmp23 = fcmp olt float %tmp5, %tmp11 143 br i1 %tmp23, label %bb26, label %bb30 144 145bb26: 146 ret i1 0 147 148bb30: 149 ret i1 1 150} 151 152; Do any-size tail-merging when two candidate blocks will both require 153; an unconditional jump to complete a two-way conditional branch. 154 155; CHECK: c_expand_expr_stmt: 156; 157; This test only works when register allocation happens to use %rax for both 158; load addresses. 159; 160; CHE: jmp .LBB3_11 161; CHE-NEXT: .LBB3_9: 162; CHE-NEXT: movq 8(%rax), %rax 163; CHE-NEXT: xorb %dl, %dl 164; CHE-NEXT: movb 16(%rax), %al 165; CHE-NEXT: cmpb $16, %al 166; CHE-NEXT: je .LBB3_11 167; CHE-NEXT: cmpb $23, %al 168; CHE-NEXT: jne .LBB3_14 169; CHE-NEXT: .LBB3_11: 170 171%0 = type { %struct.rtx_def* } 172%struct.lang_decl = type opaque 173%struct.rtx_def = type { i16, i8, i8, [1 x %union.rtunion] } 174%struct.tree_decl = type { [24 x i8], i8*, i32, %union.tree_node*, i32, i8, i8, i8, i8, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %union.tree_node*, %struct.rtx_def*, %union..2anon, %0, %union.tree_node*, %struct.lang_decl* } 175%union..2anon = type { i32 } 176%union.rtunion = type { i8* } 177%union.tree_node = type { %struct.tree_decl } 178 179define fastcc void @c_expand_expr_stmt(%union.tree_node* %expr) nounwind { 180entry: 181 %tmp4 = load i8* null, align 8 ; <i8> [#uses=3] 182 switch i8 %tmp4, label %bb3 [ 183 i8 18, label %bb 184 ] 185 186bb: ; preds = %entry 187 switch i32 undef, label %bb1 [ 188 i32 0, label %bb2.i 189 i32 37, label %bb.i 190 ] 191 192bb.i: ; preds = %bb 193 switch i32 undef, label %bb1 [ 194 i32 0, label %lvalue_p.exit 195 ] 196 197bb2.i: ; preds = %bb 198 br label %bb3 199 200lvalue_p.exit: ; preds = %bb.i 201 %tmp21 = load %union.tree_node** null, align 8 ; <%union.tree_node*> [#uses=3] 202 %tmp22 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 0 ; <i8*> [#uses=1] 203 %tmp23 = load i8* %tmp22, align 8 ; <i8> [#uses=1] 204 %tmp24 = zext i8 %tmp23 to i32 ; <i32> [#uses=1] 205 switch i32 %tmp24, label %lvalue_p.exit4 [ 206 i32 0, label %bb2.i3 207 i32 2, label %bb.i1 208 ] 209 210bb.i1: ; preds = %lvalue_p.exit 211 %tmp25 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 2 ; <i32*> [#uses=1] 212 %tmp26 = bitcast i32* %tmp25 to %union.tree_node** ; <%union.tree_node**> [#uses=1] 213 %tmp27 = load %union.tree_node** %tmp26, align 8 ; <%union.tree_node*> [#uses=2] 214 %tmp28 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1] 215 %tmp29 = load i8* %tmp28, align 8 ; <i8> [#uses=1] 216 %tmp30 = zext i8 %tmp29 to i32 ; <i32> [#uses=1] 217 switch i32 %tmp30, label %lvalue_p.exit4 [ 218 i32 0, label %bb2.i.i2 219 i32 2, label %bb.i.i 220 ] 221 222bb.i.i: ; preds = %bb.i1 223 %tmp34 = tail call fastcc i32 @lvalue_p(%union.tree_node* null) nounwind ; <i32> [#uses=1] 224 %phitmp = icmp ne i32 %tmp34, 0 ; <i1> [#uses=1] 225 br label %lvalue_p.exit4 226 227bb2.i.i2: ; preds = %bb.i1 228 %tmp35 = getelementptr inbounds %union.tree_node* %tmp27, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1] 229 %tmp36 = bitcast i8* %tmp35 to %union.tree_node** ; <%union.tree_node**> [#uses=1] 230 %tmp37 = load %union.tree_node** %tmp36, align 8 ; <%union.tree_node*> [#uses=1] 231 %tmp38 = getelementptr inbounds %union.tree_node* %tmp37, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1] 232 %tmp39 = load i8* %tmp38, align 8 ; <i8> [#uses=1] 233 switch i8 %tmp39, label %bb2 [ 234 i8 16, label %lvalue_p.exit4 235 i8 23, label %lvalue_p.exit4 236 ] 237 238bb2.i3: ; preds = %lvalue_p.exit 239 %tmp40 = getelementptr inbounds %union.tree_node* %tmp21, i64 0, i32 0, i32 0, i64 8 ; <i8*> [#uses=1] 240 %tmp41 = bitcast i8* %tmp40 to %union.tree_node** ; <%union.tree_node**> [#uses=1] 241 %tmp42 = load %union.tree_node** %tmp41, align 8 ; <%union.tree_node*> [#uses=1] 242 %tmp43 = getelementptr inbounds %union.tree_node* %tmp42, i64 0, i32 0, i32 0, i64 16 ; <i8*> [#uses=1] 243 %tmp44 = load i8* %tmp43, align 8 ; <i8> [#uses=1] 244 switch i8 %tmp44, label %bb2 [ 245 i8 16, label %lvalue_p.exit4 246 i8 23, label %lvalue_p.exit4 247 ] 248 249lvalue_p.exit4: ; preds = %bb2.i3, %bb2.i3, %bb2.i.i2, %bb2.i.i2, %bb.i.i, %bb.i1, %lvalue_p.exit 250 %tmp45 = phi i1 [ %phitmp, %bb.i.i ], [ false, %bb2.i.i2 ], [ false, %bb2.i.i2 ], [ false, %bb.i1 ], [ false, %bb2.i3 ], [ false, %bb2.i3 ], [ false, %lvalue_p.exit ] ; <i1> [#uses=1] 251 %tmp46 = icmp eq i8 %tmp4, 0 ; <i1> [#uses=1] 252 %or.cond = or i1 %tmp45, %tmp46 ; <i1> [#uses=1] 253 br i1 %or.cond, label %bb2, label %bb3 254 255bb1: ; preds = %bb2.i.i, %bb.i, %bb 256 %.old = icmp eq i8 %tmp4, 23 ; <i1> [#uses=1] 257 br i1 %.old, label %bb2, label %bb3 258 259bb2: ; preds = %bb1, %lvalue_p.exit4, %bb2.i3, %bb2.i.i2 260 br label %bb3 261 262bb3: ; preds = %bb2, %bb1, %lvalue_p.exit4, %bb2.i, %entry 263 %expr_addr.0 = phi %union.tree_node* [ null, %bb2 ], [ %expr, %bb2.i ], [ %expr, %entry ], [ %expr, %bb1 ], [ %expr, %lvalue_p.exit4 ] ; <%union.tree_node*> [#uses=0] 264 unreachable 265} 266 267declare fastcc i32 @lvalue_p(%union.tree_node* nocapture) nounwind readonly 268 269declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind 270 271 272; If one tail merging candidate falls through into the other, 273; tail merging is likely profitable regardless of how few 274; instructions are involved. This function should have only 275; one ret instruction. 276 277; CHECK: foo: 278; CHECK: callq func 279; CHECK-NEXT: .LBB4_2: 280; CHECK-NEXT: popq 281; CHECK-NEXT: ret 282 283define void @foo(i1* %V) nounwind { 284entry: 285 %t0 = icmp eq i1* %V, null 286 br i1 %t0, label %return, label %bb 287 288bb: 289 call void @func() 290 ret void 291 292return: 293 ret void 294} 295 296declare void @func() 297 298; one - One instruction may be tail-duplicated even with optsize. 299 300; CHECK: one: 301; CHECK: movl $0, XYZ(%rip) 302; CHECK: movl $0, XYZ(%rip) 303 304@XYZ = external global i32 305 306define void @one() nounwind optsize { 307entry: 308 %0 = icmp eq i32 undef, 0 309 br i1 %0, label %bbx, label %bby 310 311bby: 312 switch i32 undef, label %bb7 [ 313 i32 16, label %return 314 ] 315 316bb7: 317 volatile store i32 0, i32* @XYZ 318 unreachable 319 320bbx: 321 switch i32 undef, label %bb12 [ 322 i32 128, label %return 323 ] 324 325bb12: 326 volatile store i32 0, i32* @XYZ 327 unreachable 328 329return: 330 ret void 331} 332 333; two - Same as one, but with two instructions in the common 334; tail instead of one. This is too much to be merged, given 335; the optsize attribute. 336 337; CHECK: two: 338; CHECK-NOT: XYZ 339; CHECK: movl $0, XYZ(%rip) 340; CHECK: movl $1, XYZ(%rip) 341; CHECK-NOT: XYZ 342; CHECK: ret 343 344define void @two() nounwind optsize { 345entry: 346 %0 = icmp eq i32 undef, 0 347 br i1 %0, label %bbx, label %bby 348 349bby: 350 switch i32 undef, label %bb7 [ 351 i32 16, label %return 352 ] 353 354bb7: 355 volatile store i32 0, i32* @XYZ 356 volatile store i32 1, i32* @XYZ 357 unreachable 358 359bbx: 360 switch i32 undef, label %bb12 [ 361 i32 128, label %return 362 ] 363 364bb12: 365 volatile store i32 0, i32* @XYZ 366 volatile store i32 1, i32* @XYZ 367 unreachable 368 369return: 370 ret void 371} 372 373; two_nosize - Same as two, but without the optsize attribute. 374; Now two instructions are enough to be tail-duplicated. 375 376; CHECK: two_nosize: 377; CHECK: movl $0, XYZ(%rip) 378; CHECK: movl $1, XYZ(%rip) 379; CHECK: movl $0, XYZ(%rip) 380; CHECK: movl $1, XYZ(%rip) 381 382define void @two_nosize() nounwind { 383entry: 384 %0 = icmp eq i32 undef, 0 385 br i1 %0, label %bbx, label %bby 386 387bby: 388 switch i32 undef, label %bb7 [ 389 i32 16, label %return 390 ] 391 392bb7: 393 volatile store i32 0, i32* @XYZ 394 volatile store i32 1, i32* @XYZ 395 unreachable 396 397bbx: 398 switch i32 undef, label %bb12 [ 399 i32 128, label %return 400 ] 401 402bb12: 403 volatile store i32 0, i32* @XYZ 404 volatile store i32 1, i32* @XYZ 405 unreachable 406 407return: 408 ret void 409} 410 411; Tail-merging should merge the two ret instructions since one side 412; can fall-through into the ret and the other side has to branch anyway. 413 414; CHECK: TESTE: 415; CHECK: ret 416; CHECK-NOT: ret 417; CHECK: size TESTE 418 419define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone { 420entry: 421 %cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1] 422 %varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1] 423 %cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1] 424 br i1 %cmp410, label %for.end, label %bb.nph 425 426bb.nph: ; preds = %entry 427 %tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1] 428 ret i64 %tmp15 429 430for.end: ; preds = %entry 431 ret i64 %varx.0 432} 433