1; RUN: llc < %s -march=x86 -mattr=+sse2 > %t 2; RUN: grep shll %t | grep 12 3; RUN: grep pslldq %t | grep 12 4; RUN: grep psrldq %t | grep 8 5; RUN: grep psrldq %t | grep 12 6; There are no MMX operations in @t1 7 8define void @t1(i32 %a, x86_mmx* %P) nounwind { 9 %tmp12 = shl i32 %a, 12 10 %tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1 11 %tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0 12 %tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx 13 store x86_mmx %tmp23, x86_mmx* %P 14 ret void 15} 16 17define <4 x float> @t2(<4 x float>* %P) nounwind { 18 %tmp1 = load <4 x float>* %P 19 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 > 20 ret <4 x float> %tmp2 21} 22 23define <4 x float> @t3(<4 x float>* %P) nounwind { 24 %tmp1 = load <4 x float>* %P 25 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 > 26 ret <4 x float> %tmp2 27} 28 29define <4 x float> @t4(<4 x float>* %P) nounwind { 30 %tmp1 = load <4 x float>* %P 31 %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 > 32 ret <4 x float> %tmp2 33} 34