1; Show that we know how to translate add. 2 3; NOTE: We use -O2 to get rid of memory stores. 4 5; REQUIRES: allow_dump 6 7; Compile using standalone assembler. 8; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 9; RUN: | FileCheck %s --check-prefix=ASM 10 11; Show bytes in assembled standalone code. 12; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 13; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 14 15; Compile using integrated assembler. 16; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 17; RUN: | FileCheck %s --check-prefix=IASM 18 19; Show bytes in assembled integrated code. 20; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 21; RUN: --args -O2 | FileCheck %s --check-prefix=DIS 22 23define internal i32 @add1ToR0(i32 %p) { 24 %v = add i32 %p, 1 25 ret i32 %v 26} 27 28; ASM-LABEL: add1ToR0: 29; ASM-NEXT: .Ladd1ToR0$__0: 30; ASM-NEXT: add r0, r0, #1 31; ASM-NEXT: bx lr 32 33; DIS-LABEL:00000000 <add1ToR0>: 34; DIS-NEXT: 0: e2800001 35; DIS-NEXT: 4: e12fff1e 36 37; IASM-LABEL: add1ToR0: 38; IASM-LABEL: .Ladd1ToR0$__0: 39; IASM-NEXT: .byte 0x1 40; IASM-NEXT: .byte 0x0 41; IASM-NEXT: .byte 0x80 42; IASM-NEXT: .byte 0xe2 43 44; IASM-NEXT: .byte 0x1e 45; IASM-NEXT: .byte 0xff 46; IASM-NEXT: .byte 0x2f 47; IASM-NEXT: .byte 0xe1 48 49define internal i32 @Add2Regs(i32 %p1, i32 %p2) { 50 %v = add i32 %p1, %p2 51 ret i32 %v 52} 53 54; ASM-LABEL: Add2Regs: 55; ASM-NEXT: .LAdd2Regs$__0: 56; ASM-NEXT: add r0, r0, r1 57; ASM-NEXT: bx lr 58 59; DIS-LABEL:00000010 <Add2Regs>: 60; DIS-NEXT: 10: e0800001 61; DIS-NEXT: 14: e12fff1e 62 63; IASM-LABEL: Add2Regs: 64; IASM-NEXT: .LAdd2Regs$__0: 65; IASM-NEXT: .byte 0x1 66; IASM-NEXT: .byte 0x0 67; IASM-NEXT: .byte 0x80 68; IASM-NEXT: .byte 0xe0 69 70; IASM-NEXT: .byte 0x1e 71; IASM-NEXT: .byte 0xff 72; IASM-NEXT: .byte 0x2f 73; IASM-NEXT: .byte 0xe1 74 75define internal i64 @addI64ToR0R1(i64 %p) { 76 %v = add i64 %p, 1 77 ret i64 %v 78} 79 80; ASM-LABEL:addI64ToR0R1: 81; ASM-NEXT:.LaddI64ToR0R1$__0: 82; ASM-NEXT: adds r0, r0, #1 83; ASM-NEXT: adc r1, r1, #0 84 85; DIS-LABEL:00000020 <addI64ToR0R1>: 86; DIS-NEXT: 20: e2900001 87; DIS-NEXT: 24: e2a11000 88 89; IASM-LABEL:addI64ToR0R1: 90; IASM-NEXT:.LaddI64ToR0R1$__0: 91; IASM-NEXT: .byte 0x1 92; IASM-NEXT: .byte 0x0 93; IASM-NEXT: .byte 0x90 94; IASM-NEXT: .byte 0xe2 95; IASM-NEXT: .byte 0x0 96; IASM-NEXT: .byte 0x10 97; IASM-NEXT: .byte 0xa1 98; IASM-NEXT: .byte 0xe2 99 100define internal i64 @AddI64Regs(i64 %p1, i64 %p2) { 101 %v = add i64 %p1, %p2 102 ret i64 %v 103} 104 105; ASM-LABEL:AddI64Regs: 106; ASM-NEXT:.LAddI64Regs$__0: 107; ASM-NEXT: adds r0, r0, r2 108; ASM-NEXT: adc r1, r1, r3 109 110; DIS-LABEL:00000030 <AddI64Regs>: 111; DIS-NEXT: 30: e0900002 112; DIS-NEXT: 34: e0a11003 113 114; IASM-LABEL:AddI64Regs: 115; IASM-NEXT:.LAddI64Regs$__0: 116; IASM-NEXT: .byte 0x2 117; IASM-NEXT: .byte 0x0 118; IASM-NEXT: .byte 0x90 119; IASM-NEXT: .byte 0xe0 120; IASM-NEXT: .byte 0x3 121; IASM-NEXT: .byte 0x10 122; IASM-NEXT: .byte 0xa1 123; IASM-NEXT: .byte 0xe0 124