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1 /* ----------------------------------------------------------------------- *
2  *
3  *   Copyright 2009-2011 Erwan Velu - All Rights Reserved
4  *
5  *   This program is free software; you can redistribute it and/or modify
6  *   it under the terms of the GNU General Public License as published by
7  *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
8  *   Boston MA 02111-1307, USA; either version 2 of the License, or
9  *   (at your option) any later version; incorporated herein by reference.
10  *
11  * ----------------------------------------------------------------------- */
12 
13 #ifndef FADT_H
14 #define FADT_H
15 #include <inttypes.h>
16 #include <stdbool.h>
17 
18 enum { FADT_TABLE_FOUND = 1};
19 
20 #define FACP "FACP"
21 #define FADT "FADT"
22 
23 /* prefered pm profiles */
24 enum { PM_UNSPECIFIED = 0,
25     PM_DESKTOP = 1,
26     PM_MOBILE = 2,
27     PM_WORKSTATION = 3,
28     PM_ENTERPRISE_SERVER = 4,
29     PM_SOHO_SERVER = 5,
30     PM_APPLIANCE_PC = 6,
31     PM_PERFORMANCE_SERVER = 7
32 };
33 
34 /* iapc_boot_arch flags*/
35 #define IAPC_LEGAGY_DEVICE 1
36 #define IAPC_8042 1<<1
37 #define IAPC_VGA_NOT_PRESENT 1<<2
38 #define IAPC_MSI_NOT_SUPPORTED 1<<3
39 #define IAPC_PCIE_ASPM_CONTROLS 1<<4
40 
41 /* feature flags for "flags" */
42 #define WBINVD 1
43 #define WBINVD_FLUSH 1<<1
44 #define PROC_C1 1<<2
45 #define P_LVL2_UP 1<<3
46 #define PWR_BUTTON 1<<4
47 #define SLP_BUTTON 1<<5
48 #define FIX_RTC 1<<6
49 #define RTC_S4 1<<7
50 #define TMR_VAL_EXT 1<<8
51 #define DCK_CAP 1<<9
52 #define RESET_REG_SUP 1<<10
53 #define SEALED_CASE 1<<11
54 #define HEADLESS 1<<12
55 #define CPU_SW_SLP 1<<13
56 #define PCI_EXP_WAK 1<<14
57 #define USE_PLATEFORM_CLOCK 1<<15
58 #define S4_RTC_STS_VALID 1<<16
59 #define REMOTE_POWER_ON_CAPABLE 1<<17
60 #define FORCE_APIC_CLUSTER_MODEL 1<<18
61 #define FORCE_APIC_PHYSICAL_DESTINATION_MODE 1<<19
62 
63 typedef struct {
64     uint64_t *address;
65     s_acpi_description_header header;
66     bool valid;
67     uint32_t *firmware_ctrl;
68     uint32_t *dsdt_address;
69     uint8_t reserved;
70     uint8_t prefered_pm_profile;
71     uint16_t sci_int;
72     uint32_t smi_cmd;
73     uint8_t acpi_enable;
74     uint8_t acpi_disable;
75     uint8_t s4bios_req;
76     uint8_t pstate_cnt;
77     uint32_t pm1a_evt_blk;
78     uint32_t pm1b_evt_blk;
79     uint32_t pm1a_cnt_blk;
80     uint32_t pm1b_cnt_blk;
81     uint32_t pm2_cnt_blk;
82     uint32_t pm_tmr_blk;
83     uint32_t gpe0_blk;
84     uint32_t gpe1_blk;
85     uint8_t pm1_evt_len;
86     uint8_t pm1_cnt_len;
87     uint8_t pm2_cnt_len;
88     uint8_t pm_tmr_len;
89     uint8_t gpe0_blk_len;
90     uint8_t gpe1_blk_len;
91     uint8_t gpe1_base;
92     uint8_t cst_cnt;
93     uint16_t p_lvl2_lat;
94     uint16_t p_lvl3_lat;
95     uint16_t flush_size;
96     uint16_t flush_stride;
97     uint8_t duty_offset;
98     uint8_t duty_width;
99     uint8_t day_alarm;
100     uint8_t mon_alarm;
101     uint8_t century;
102     uint16_t iapc_boot_arch;
103     uint8_t reserved_2;
104     uint32_t flags;
105     s_gas reset_reg;
106     uint8_t reset_value;
107     uint8_t reserved_3[3];
108     uint64_t *x_firmware_ctrl;
109     uint64_t *x_dsdt;
110     s_gas x_pm1a_evt_blk;
111     s_gas x_pm1b_evt_blk;
112     s_gas x_pm1a_cnt_blk;
113     s_gas x_pm1b_cnt_blk;
114     s_gas x_pm2_cnt_blk;
115     s_gas x_pm_tmr_blk;
116     s_gas x_gpe0_blk;
117     s_gas x_gpe1_blk;
118 } s_fadt;
119 
120 void parse_fadt(s_fadt * fadt);
121 #endif
122