callgrind/tests/simwork-both.stderr.exp

Events    : Ir Dr Dw I1mr D1mr D1mw ILmr DLmr DLmw Bc Bcm Bi Bim
Collected :

I   refs:
I1  misses:
LLi misses:
I1  miss rate:
LLi miss rate:

D   refs:
D1  misses:
LLd misses:
D1  miss rate:
LLd miss rate:

LL refs:
LL misses:
LL miss rate:

Branches:
Mispredicts:
Mispred rate: