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Searched defs:RC (Results 1 – 25 of 290) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in mask() local
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
218 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
219 -> BT::RegisterCell { in evaluate()
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
279 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
300 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate() local
309 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
[all …]
/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp41 const TargetRegisterClass *RC = in getGlobalBaseReg() local
58 const TargetRegisterClass *RC = in createEhDataRegsFI() local
73 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in createISRRegFI() local
96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
356 const TargetRegisterClass *RC = in expandExtractElementF64() local
395 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
695 const TargetRegisterClass *RC = in emitEpilogue() local
812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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DMipsInstrInfo.h100 const TargetRegisterClass *RC, in storeRegToStackSlot()
108 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DIRBuilder.h503 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
516 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
523 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
536 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
543 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
556 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
563 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
575 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
586 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
592 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
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/external/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterClassInfo.h64 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
80 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
87 ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const { in getOrder()
97 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
DLiveStackAnalysis.cpp55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
/external/llvm/include/llvm/IR/
DIRBuilder.h781 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
795 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
803 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
817 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
825 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
839 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
847 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
859 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
871 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
878 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.cpp162 const TargetRegisterClass *RC) { in inClass()
175 const TargetRegisterClass *RC, in storeRegToStackSlot()
212 const TargetRegisterClass *RC, in storeRegToAddr()
222 const TargetRegisterClass *RC, in loadRegFromStackSlot()
253 const TargetRegisterClass *RC, in loadRegFromAddr()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h142 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
148 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
155 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
383 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
396 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, in canCombineSubRegIndices()
482 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
491 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { in getLargestLegalSuperClass()
500 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
512 getRawAllocationOrder(const TargetRegisterClass *RC, in getRawAllocationOrder()
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/external/llvm/lib/CodeGen/
DLiveStackAnalysis.cpp58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
/external/swiftshader/third_party/LLVM/utils/TableGen/
DRegisterInfoEmitter.cpp340 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runMCDesc() local
455 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetHeader() local
503 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
514 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
548 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
561 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
592 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
604 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; in runTargetDesc() local
620 const CodeGenRegisterClass &RC = *RegisterClasses[i]; in runTargetDesc() local
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/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp463 const TargetRegisterClass *RC, in PPCEmitLoad()
609 const TargetRegisterClass *RC = in SelectLoad() local
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
988 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1095 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1184 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1346 const TargetRegisterClass *RC = in processCallArgs() local
1358 const TargetRegisterClass *RC = in processCallArgs() local
1675 const TargetRegisterClass *RC = in SelectRet() local
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/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h144 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
149 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
156 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
500 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
535 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg()
682 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
691 getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
704 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
888 const TargetRegisterClass *RC, in saveScavengerRegister()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DFastISel.cpp592 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in SelectCall() local
616 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); in SelectCall() local
1098 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { in createResultReg()
1103 const TargetRegisterClass* RC) { in FastEmitInst_()
1112 const TargetRegisterClass *RC, in FastEmitInst_r()
1131 const TargetRegisterClass *RC, in FastEmitInst_rr()
1152 const TargetRegisterClass *RC, in FastEmitInst_rrr()
1176 const TargetRegisterClass *RC, in FastEmitInst_ri()
1197 const TargetRegisterClass *RC, in FastEmitInst_rii()
1220 const TargetRegisterClass *RC, in FastEmitInst_rf()
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/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp133 for (const auto &RC : RegisterClasses) in runEnums() local
199 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
989 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1029 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1144 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1181 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1190 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1244 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1271 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1286 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
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/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dinstructions.h33 #define __PASTE(RA, RB, L, RC) \ argument
35 #define PASTE(RA, RB, L, RC) \ argument
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb1InstrInfo.cpp48 const TargetRegisterClass *RC, in storeRegToStackSlot()
77 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetRegisterInfo.cpp62 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
75 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp48 const TargetRegisterClass *RC, in storeRegToStackSlot()
66 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp73 const TargetRegisterClass *RC, in storeRegToStackSlot()
99 const TargetRegisterClass *RC, in loadRegFromStackSlot()

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