1 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the live stack slot analysis pass. It is analogous to
11 // live interval analysis except it's analyzing liveness of stack slots rather
12 // than registers.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #define DEBUG_TYPE "livestacks"
17 #include "llvm/CodeGen/LiveStackAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/Statistic.h"
24 #include <limits>
25 using namespace llvm;
26
27 char LiveStacks::ID = 0;
28 INITIALIZE_PASS(LiveStacks, "livestacks",
29 "Live Stack Slot Analysis", false, false)
30
31 char &llvm::LiveStacksID = LiveStacks::ID;
32
getAnalysisUsage(AnalysisUsage & AU) const33 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
34 AU.setPreservesAll();
35 AU.addPreserved<SlotIndexes>();
36 AU.addRequiredTransitive<SlotIndexes>();
37 MachineFunctionPass::getAnalysisUsage(AU);
38 }
39
releaseMemory()40 void LiveStacks::releaseMemory() {
41 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
42 VNInfoAllocator.Reset();
43 S2IMap.clear();
44 S2RCMap.clear();
45 }
46
runOnMachineFunction(MachineFunction & MF)47 bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
48 TRI = MF.getTarget().getRegisterInfo();
49 // FIXME: No analysis is being done right now. We are relying on the
50 // register allocators to provide the information.
51 return false;
52 }
53
54 LiveInterval &
getOrCreateInterval(int Slot,const TargetRegisterClass * RC)55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
56 assert(Slot >= 0 && "Spill slot indice must be >= 0");
57 SS2IntervalMap::iterator I = S2IMap.find(Slot);
58 if (I == S2IMap.end()) {
59 I = S2IMap.insert(I, std::make_pair(Slot,
60 LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F)));
61 S2RCMap.insert(std::make_pair(Slot, RC));
62 } else {
63 // Use the largest common subclass register class.
64 const TargetRegisterClass *OldRC = S2RCMap[Slot];
65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
66 }
67 return I->second;
68 }
69
70 /// print - Implement the dump method.
print(raw_ostream & OS,const Module *) const71 void LiveStacks::print(raw_ostream &OS, const Module*) const {
72
73 OS << "********** INTERVALS **********\n";
74 for (const_iterator I = begin(), E = end(); I != E; ++I) {
75 I->second.print(OS);
76 int Slot = I->first;
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
78 if (RC)
79 OS << " [" << RC->getName() << "]\n";
80 else
81 OS << " [Unknown]\n";
82 }
83 }
84