| /art/runtime/arch/mips/ |
| D | registers_mips.h | 48 S1 = 17, enumerator
63 TR = S1, // ART Thread Register
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| D | quick_method_frame_info_mips.h | 55 (1 << art::mips::ZERO) | (1 << art::mips::S0) | (1 << art::mips::S1);
61 (1 << art::mips::S0) | (1 << art::mips::S1) | (1 << art::mips::T8) | (1 << art::mips::T9);
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 48 S1 = 17, enumerator
63 TR = S1, // ART Thread Register
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| D | quick_method_frame_info_mips64.h | 41 (1 << art::mips64::S0) | (1 << art::mips64::S1);
48 (1 << art::mips64::S0) | (1 << art::mips64::S1) | (1 << art::mips64::T8) |
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 78 reg = ArmManagedRegister::FromSRegister(S1); in TEST()
85 EXPECT_EQ(S1, reg.AsSRegister()); in TEST()
135 EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh()); in TEST()
312 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
322 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
331 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
336 ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1); in TEST()
341 EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
465 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
487 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
[all …]
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 182 sreg = Arm64ManagedRegister::FromSRegister(S1); in TEST()
190 EXPECT_EQ(S1, reg.AsOverlappingSRegister()); in TEST()
295 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
311 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
321 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
329 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
333 Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1); in TEST()
339 EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
388 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
410 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
[all …]
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 59 S1 = 1, enumerator
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| D | context_arm.cc | 83 fprs_[S1] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 46 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 155 S1 = 1, enumerator
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 152 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value()); in CreateTrampoline()
184 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); in CreateTrampoline()
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 49 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 53 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/mips64/ |
| D | managed_register_mips64_test.cc | 231 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromGpuRegister(S1))); in TEST()
260 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::FromGpuRegister(S1))); in TEST()
270 EXPECT_FALSE(reg_W31.Equals(Mips64ManagedRegister::FromGpuRegister(S1))); in TEST()
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| D | assembler_mips64.cc | 3730 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in StoreStackOffsetToThread()
3734 StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread()
3751 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread()
3782 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread()
3828 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in CopyRawPtrFromThread()
3840 S1, thr_offs.Int32Value()); in CopyRawPtrToThread()
4042 Move(tr.AsMips64().AsGpuRegister(), S1); in GetCurrentThread()
4047 StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value()); in GetCurrentThread()
4055 S1, in ExceptionPoll()
4072 S1, in EmitExceptionPoll()
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| D | assembler_mips64_test.cc | 109 registers_.push_back(new mips64::GpuRegister(mips64::S1)); in SetUpHelpers()
142 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S1), "s1"); in SetUpHelpers()
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| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 98 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
131 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()
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| D | assembler_mips.cc | 4912 S1, thr_offs.Int32Value()); in StoreStackOffsetToThread()
4916 StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread()
4933 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread()
4963 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread()
5020 S1, thr_offs.Int32Value()); in CopyRawPtrFromThread()
5033 S1, thr_offs.Int32Value()); in CopyRawPtrToThread()
5205 Move(tr.AsMips().AsCoreRegister(), S1); in GetCurrentThread()
5210 StoreToOffset(kStoreWord, S1, SP, offset.Int32Value()); in GetCurrentThread()
5217 S1, Thread::ExceptionOffset<kMipsPointerSize>().Int32Value()); in ExceptionPoll()
5231 LoadFromOffset(kLoadWord, T9, S1, in EmitExceptionPoll()
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| D | assembler_mips32r6_test.cc | 111 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
144 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()
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| D | assembler_mips_test.cc | 79 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
112 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
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| D | code_generator_mips.h | 57 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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