| /art/runtime/arch/arm/ |
| D | registers_arm.h | 61 S3 = 3, enumerator
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| D | context_arm.cc | 85 fprs_[S3] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 46 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 50 S3 = 19, enumerator
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| D | quick_method_frame_info_mips.h | 33 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 50 S3 = 19, enumerator
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| D | quick_method_frame_info_mips64.h | 33 (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 157 S3 = 3, enumerator
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 41 Mips64ManagedRegister::FromGpuRegister(S3),
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 53 MipsManagedRegister::FromCoreRegister(S3),
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 49 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 53 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 100 registers_.push_back(new mips::Register(mips::S3)); in SetUpHelpers()
133 secondary_register_names_.emplace(mips::Register(mips::S3), "s3"); in SetUpHelpers()
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| D | assembler_mips32r6_test.cc | 113 registers_.push_back(new mips::Register(mips::S3)); in SetUpHelpers()
146 secondary_register_names_.emplace(mips::Register(mips::S3), "s3"); in SetUpHelpers()
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| D | assembler_mips_test.cc | 81 registers_.push_back(new mips::Register(mips::S3)); in SetUpHelpers()
114 secondary_register_names_.emplace(mips::Register(mips::S3), "s3"); in SetUpHelpers()
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 87 reg = ArmManagedRegister::FromSRegister(S3); in TEST()
94 EXPECT_EQ(S3, reg.AsSRegister()); in TEST()
147 EXPECT_EQ(S3, reg.AsOverlappingDRegisterHigh()); in TEST()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
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| D | code_generator_mips.h | 57 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 709 EXPECT_TRUE(vixl::aarch64::s3.Is(Arm64Assembler::reg_s(S3))); in TEST()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 111 registers_.push_back(new mips64::GpuRegister(mips64::S3)); in SetUpHelpers()
144 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S3), "s3"); in SetUpHelpers()
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