| /art/runtime/arch/arm/ |
| D | registers_arm.h | 64 S6 = 6, enumerator
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| D | context_arm.cc | 88 fprs_[S6] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 47 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 53 S6 = 22, enumerator
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| D | quick_method_frame_info_mips.h | 34 (1 << art::mips::S6) | (1 << art::mips::S7) | (1 << art::mips::GP) | (1 << art::mips::FP);
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 53 S6 = 22, enumerator
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| D | quick_method_frame_info_mips64.h | 34 (1 << art::mips64::S5) | (1 << art::mips64::S6) | (1 << art::mips64::S7) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 160 S6 = 6, enumerator
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 44 Mips64ManagedRegister::FromGpuRegister(S6),
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 56 MipsManagedRegister::FromCoreRegister(S6),
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 49 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 53 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 103 registers_.push_back(new mips::Register(mips::S6)); in SetUpHelpers()
136 secondary_register_names_.emplace(mips::Register(mips::S6), "s6"); in SetUpHelpers()
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| D | assembler_mips32r6_test.cc | 116 registers_.push_back(new mips::Register(mips::S6)); in SetUpHelpers()
149 secondary_register_names_.emplace(mips::Register(mips::S6), "s6"); in SetUpHelpers()
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| D | assembler_mips_test.cc | 84 registers_.push_back(new mips::Register(mips::S6)); in SetUpHelpers()
117 secondary_register_names_.emplace(mips::Register(mips::S6), "s6"); in SetUpHelpers()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
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| D | code_generator_mips.h | 57 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 712 EXPECT_TRUE(vixl::aarch64::s6.Is(Arm64Assembler::reg_s(S6))); in TEST()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 114 registers_.push_back(new mips64::GpuRegister(mips64::S6)); in SetUpHelpers()
147 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S6), "s6"); in SetUpHelpers()
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