| /art/runtime/arch/arm/ |
| D | registers_arm.h | 65 S7 = 7, enumerator
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| D | context_arm.cc | 89 fprs_[S7] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 47 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 54 S7 = 23, enumerator
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| D | quick_method_frame_info_mips.h | 34 (1 << art::mips::S6) | (1 << art::mips::S7) | (1 << art::mips::GP) | (1 << art::mips::FP);
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 54 S7 = 23, enumerator
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| D | quick_method_frame_info_mips64.h | 34 (1 << art::mips64::S5) | (1 << art::mips64::S6) | (1 << art::mips64::S7) |
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 161 S7 = 7, enumerator
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 45 Mips64ManagedRegister::FromGpuRegister(S7),
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 57 MipsManagedRegister::FromCoreRegister(S7),
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 49 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 53 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/mips/ |
| D | assembler_mips32r5_test.cc | 104 registers_.push_back(new mips::Register(mips::S7)); in SetUpHelpers()
137 secondary_register_names_.emplace(mips::Register(mips::S7), "s7"); in SetUpHelpers()
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| D | assembler_mips32r6_test.cc | 117 registers_.push_back(new mips::Register(mips::S7)); in SetUpHelpers()
150 secondary_register_names_.emplace(mips::Register(mips::S7), "s7"); in SetUpHelpers()
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| D | assembler_mips_test.cc | 85 registers_.push_back(new mips::Register(mips::S7)); in SetUpHelpers()
118 secondary_register_names_.emplace(mips::Register(mips::S7), "s7"); in SetUpHelpers()
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 244 reg = Arm64ManagedRegister::FromSRegister(S7); in TEST()
252 EXPECT_EQ(S7, reg.AsSRegister()); in TEST()
254 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S7))); in TEST()
713 EXPECT_TRUE(vixl::aarch64::s7.Is(Arm64Assembler::reg_s(S7))); in TEST()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA };
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| D | code_generator_mips.h | 57 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| D | code_generator_mips64.cc | 510 (S2 <= ref_reg && ref_reg <= S7) || in EmitNativeCode()
609 (S2 <= ref_reg && ref_reg <= S7) || in EmitNativeCode()
5020 } else if (reg >= S2 && reg <= S7) { // 6 consequtive regs. in GetBakerMarkThunkNumber()
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| D | code_generator_mips.cc | 553 (S2 <= ref_reg && ref_reg <= S7) || in EmitNativeCode()
653 (S2 <= ref_reg && ref_reg <= S7) || in EmitNativeCode()
6850 } else if (reg >= S2 && reg <= S7) { // 6 consequtive regs. in GetBakerMarkThunkNumber()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 115 registers_.push_back(new mips64::GpuRegister(mips64::S7)); in SetUpHelpers()
148 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S7), "s7"); in SetUpHelpers()
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