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Searched refs:ARM (Results 1 – 25 of 1033) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), in ARMBaseRegisterInfo()
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
61 BasePtr(ARM::R6) { in ARMBaseRegisterInfo()
74 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
75 ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
77 ARM::D15, ARM::D14, ARM::D13, ARM::D12, in getCalleeSavedRegs()
78 ARM::D11, ARM::D10, ARM::D9, ARM::D8, in getCalleeSavedRegs()
85 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
86 ARM::R11, ARM::R10, ARM::R8, in getCalleeSavedRegs()
88 ARM::D15, ARM::D14, ARM::D13, ARM::D12, in getCalleeSavedRegs()
[all …]
DARMExpandPseudoInsts.cpp125 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4},
126 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4},
127 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2},
128 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2},
129 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8},
130 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8},
132 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 },
133 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 },
134 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 },
135 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 },
[all …]
DARMBaseInstrInfo.cpp65 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
66 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
67 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
68 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
69 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
72 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
75 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
76 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DThumb2SizeReduction.cpp59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 },
60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 },
61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 },
70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 },
[all …]
DThumb2InstrInfo.cpp74 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || in storeRegToStackSlot()
125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass || in storeRegToStackSlot()
126 RC == ARM::GPRnopcRegisterClass) { in storeRegToStackSlot()
138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
152 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || in loadRegFromStackSlot()
153 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass || in loadRegFromStackSlot()
154 RC == ARM::GPRnopcRegisterClass) { in loadRegFromStackSlot()
[all …]
DARMInstrInfo.cpp33 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
34 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
35 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
36 case ARM::LDR_POST_REG: in getUnindexedOpcode()
37 return ARM::LDRi12; in getUnindexedOpcode()
38 case ARM::LDRH_PRE: in getUnindexedOpcode()
39 case ARM::LDRH_POST: in getUnindexedOpcode()
40 return ARM::LDRH; in getUnindexedOpcode()
41 case ARM::LDRB_PRE_IMM: in getUnindexedOpcode()
42 case ARM::LDRB_PRE_REG: in getUnindexedOpcode()
[all …]
DARMLoadStoreOptimizer.cpp135 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
139 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
140 case ARM_AM::da: return ARM::LDMDA; in getLoadStoreMultipleOpcode()
141 case ARM_AM::db: return ARM::LDMDB; in getLoadStoreMultipleOpcode()
142 case ARM_AM::ib: return ARM::LDMIB; in getLoadStoreMultipleOpcode()
145 case ARM::STRi12: in getLoadStoreMultipleOpcode()
149 case ARM_AM::ia: return ARM::STMIA; in getLoadStoreMultipleOpcode()
150 case ARM_AM::da: return ARM::STMDA; in getLoadStoreMultipleOpcode()
151 case ARM_AM::db: return ARM::STMDB; in getLoadStoreMultipleOpcode()
152 case ARM_AM::ib: return ARM::STMIB; in getLoadStoreMultipleOpcode()
[all …]
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
[all …]
DARMFeatures.h29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
37 case ARM::tEOR: in isV8EligibleForIT()
38 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
70 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
72 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
73 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
76 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
77 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DThumb2SizeReduction.cpp64 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
65 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
66 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
67 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
68 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
69 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
70 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
71 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
72 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
75 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
DThumb2InstrInfo.cpp37 NopInst.setOpcode(ARM::tHINT); in getNoopForMachoTarget()
79 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in storeRegToStackSlot()
140 RC == &ARM::GPRnopcRegClass) { in storeRegToStackSlot()
141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
153 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
[all …]
DARMInstrInfo.cpp38 NopInst.setOpcode(ARM::HINT); in getNoopForMachoTarget()
43 NopInst.setOpcode(ARM::MOVr); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
56 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
57 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
58 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
59 case ARM::LDR_POST_REG: in getUnindexedOpcode()
60 return ARM::LDRi12; in getUnindexedOpcode()
61 case ARM::LDRH_PRE: in getUnindexedOpcode()
[all …]
DARMLoadStoreOptimizer.cpp181 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
192 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
196 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
197 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
198 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
199 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
203 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
204 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
229 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
233 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
[all …]
/external/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 … < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 … %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
24 ; ARM-linux-NEXT: blo .LBB0_2
26 ; ARM-linux: mov r4, #48
[all …]
Ddebug-frame-large-stack.ll1 …=asm -o - < %s -mtriple arm-arm-netbsd-eabi -disable-fp-elim| FileCheck %s --check-prefix=CHECK-ARM
2 …filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK-ARM-FP-ELIM
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
/external/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/llvm/lib/Support/
DTargetParser.cpp23 using namespace ARM;
35 ARM::FPUKind ID;
36 ARM::FPUVersion FPUVersion;
37 ARM::NeonSupportLevel NeonSupport;
38 ARM::FPURestriction Restriction;
64 ARM::ArchKind ID;
128 ARM::ArchKind ArchID;
149 StringRef llvm::ARM::getFPUName(unsigned FPUKind) { in getFPUName()
150 if (FPUKind >= ARM::FK_LAST) in getFPUName()
155 unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
[all …]
/external/swiftshader/third_party/llvm-subzero/lib/Support/
DTargetParser.cpp23 using namespace ARM;
35 ARM::FPUKind ID;
36 ARM::FPUVersion FPUVersion;
37 ARM::NeonSupportLevel NeonSupport;
38 ARM::FPURestriction Restriction;
75 ArchNames<ARM::ArchKind> ARCHNames[] = {
138 CpuNames<ARM::ArchKind> CPUNames[] = {
156 StringRef llvm::ARM::getFPUName(unsigned FPUKind) { in getFPUName()
157 if (FPUKind >= ARM::FK_LAST) in getFPUName()
162 unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
[all …]
/external/llvm/unittests/Support/
DTargetParserTest.cpp19 llvm::ARM::ID,
31 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0); in TEST()
32 AK <= ARM::ArchKind::AK_LAST; in TEST()
33 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1)) in TEST()
34 EXPECT_TRUE(AK == ARM::AK_LAST ? ARM::getArchName(AK).empty() in TEST()
35 : !ARM::getArchName(AK).empty()); in TEST()
39 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0); in TEST()
40 AK <= ARM::ArchKind::AK_LAST; in TEST()
41 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1)) in TEST()
42 EXPECT_TRUE((AK == ARM::AK_INVALID || AK == ARM::AK_LAST) in TEST()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp422 case ARM::HVC: { in checkDecodedInstruction()
442 assert(!STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
581 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
586 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
602 case ARM::tBcc: in AddThumbPredicate()
603 case ARM::t2Bcc: in AddThumbPredicate()
604 case ARM::tCBZ: in AddThumbPredicate()
605 case ARM::tCBNZ: in AddThumbPredicate()
606 case ARM::tCPS: in AddThumbPredicate()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.cpp52 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
102 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
175 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
176 bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode()
181 case ARM::tBcc: in getRelaxedOpcode()
182 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
183 case ARM::tLDRpci: in getRelaxedOpcode()
184 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
185 case ARM::tADR: in getRelaxedOpcode()
186 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; in getRelaxedOpcode()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && in getInstruction()
571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
592 case ARM::tBcc: in AddThumbPredicate()
593 case ARM::t2Bcc: in AddThumbPredicate()
594 case ARM::tCBZ: in AddThumbPredicate()
595 case ARM::tCBNZ: in AddThumbPredicate()
596 case ARM::tCPS: in AddThumbPredicate()
597 case ARM::t2CPS3p: in AddThumbPredicate()
[all …]
/external/llvm/test/MC/ARM/
Ddata-in-code.ll3 ;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s
36 ;; ARM: Symbol {
37 ;; ARM: Name: $a
38 ;; ARM-NEXT: Value: 0x0
39 ;; ARM-NEXT: Size: 0
40 ;; ARM-NEXT: Binding: Local
41 ;; ARM-NEXT: Type: None
42 ;; ARM-NEXT: Other:
43 ;; ARM-NEXT: Section: [[MIXED_SECT:[^ ]+]]
45 ;; ARM: Symbol {
[all …]

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