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Searched refs:DCI (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h70 SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
71 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
72 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
73 SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
74 SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
75 SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
76 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
78 SDValue RHS, DAGCombinerInfo &DCI) const;
79 SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
163 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
[all …]
DSIISelLowering.h56 DAGCombinerInfo &DCI) const;
59 DAGCombinerInfo &DCI) const;
60 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
61 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
62 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
63 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
65 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
67 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
138 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
DAMDGPUISelLowering.cpp955 DAGCombinerInfo &DCI) const { in CombineFMinMaxLegacy()
962 SelectionDAG &DAG = DCI.DAG; in CombineFMinMaxLegacy()
992 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && in CombineFMinMaxLegacy()
993 !DCI.isCalledByLegalizer()) in CombineFMinMaxLegacy()
1013 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG && in CombineFMinMaxLegacy()
1014 !DCI.isCalledByLegalizer()) in CombineFMinMaxLegacy()
2136 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { in simplifyI24() argument
2138 SelectionDAG &DAG = DCI.DAG; in simplifyI24()
2146 DCI.CommitTargetLoweringOpt(TLO); in simplifyI24()
2194 DAGCombinerInfo &DCI) const { in performLoadCombine()
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DSIISelLowering.cpp2414 DAGCombinerInfo &DCI) const { in performUCharToFloatCombine()
2420 SelectionDAG &DAG = DCI.DAG; in performUCharToFloatCombine()
2430 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) { in performUCharToFloatCombine()
2433 DCI.AddToWorklist(Cvt.getNode()); in performUCharToFloatCombine()
2486 DAGCombinerInfo &DCI) const { in performSHLPtrCombine()
2507 SelectionDAG &DAG = DCI.DAG; in performSHLPtrCombine()
2518 DAGCombinerInfo &DCI) const { in performAndCombine()
2519 if (DCI.isBeforeLegalize()) in performAndCombine()
2522 if (SDValue Base = AMDGPUTargetLowering::performAndCombine(N, DCI)) in performAndCombine()
2525 SelectionDAG &DAG = DCI.DAG; in performAndCombine()
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DR600ISelLowering.h35 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.h479 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
544 unsigned Index, DAGCombinerInfo &DCI,
547 DAGCombinerInfo &DCI) const;
548 SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
549 SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
550 SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
551 SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
552 SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
553 SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
554 SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
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DSystemZISelLowering.cpp4717 DAGCombinerInfo &DCI, in combineExtract() argument
4719 SelectionDAG &DAG = DCI.DAG; in combineExtract()
4769 DCI.AddToWorklist(Op.getNode()); in combineExtract()
4774 DCI.AddToWorklist(Op.getNode()); in combineExtract()
4809 DCI.AddToWorklist(Op.getNode()); in combineExtract()
4820 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const { in combineTruncateExtract()
4846 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true); in combineTruncateExtract()
4855 SDNode *N, DAGCombinerInfo &DCI) const { in combineSIGN_EXTEND()
4859 SelectionDAG &DAG = DCI.DAG; in combineSIGN_EXTEND()
4886 SDNode *N, DAGCombinerInfo &DCI) const { in combineMERGE()
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h554 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
555 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
557 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
925 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
926 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
927 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
928 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
930 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
933 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp6377 TargetLowering::DAGCombinerInfo &DCI) { in combineSelectAndUse() argument
6378 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
6438 TargetLowering::DAGCombinerInfo &DCI, in AddCombineToVPADDL() argument
6443 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineToVPADDL()
6497 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL()
6529 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombineWithOperands() argument
6533 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); in PerformADDCombineWithOperands()
6539 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); in PerformADDCombineWithOperands()
6548 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombine() argument
6554 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); in PerformADDCombine()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp8679 TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUse() argument
8681 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
8705 TargetLowering::DAGCombinerInfo &DCI) { in combineSelectAndUseCommutative() argument
8709 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
8712 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
8720 TargetLowering::DAGCombinerInfo &DCI, in AddCombineToVPADDL() argument
8725 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() in AddCombineToVPADDL()
8779 SelectionDAG &DAG = DCI.DAG; in AddCombineToVPADDL()
8818 TargetLowering::DAGCombinerInfo &DCI, in AddCombineTo64bitMLAL() argument
8924 SelectionDAG &DAG = DCI.DAG; in AddCombineTo64bitMLAL()
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/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1283 DAGCombinerInfo &DCI, in simplifySetCCWithAnd() argument
1307 SelectionDAG &DAG = DCI.DAG; in simplifySetCCWithAnd()
1315 if (DCI.isBeforeLegalizeOps() || in simplifySetCCWithAnd()
1344 DAGCombinerInfo &DCI, in SimplifySetCC() argument
1346 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
1367 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1426 DCI.isBeforeLegalize() && N0->hasOneUse()) { in SimplifySetCC()
1512 if (DCI.isBeforeLegalize() && in SimplifySetCC()
1605 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
1642 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp4562 const AArch64TargetLowering::DAGCombinerInfo &DCI, unsigned Opcode, in getEstimate() argument
4574 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getEstimate()
4579 return DCI.DAG.getNode(Opcode, SDLoc(Operand), VT, Operand); in getEstimate()
4583 DAGCombinerInfo &DCI, unsigned &ExtraSteps) const { in getRecipEstimate() argument
4584 return getEstimate(*Subtarget, DCI, AArch64ISD::FRECPE, Operand, ExtraSteps); in getRecipEstimate()
4588 DAGCombinerInfo &DCI, unsigned &ExtraSteps, bool &UseOneConst) const { in getRsqrtEstimate() argument
4590 return getEstimate(*Subtarget, DCI, AArch64ISD::FRSQRTE, Operand, ExtraSteps); in getRsqrtEstimate()
7481 TargetLowering::DAGCombinerInfo &DCI, in performXorCombine() argument
7483 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
7539 TargetLowering::DAGCombinerInfo &DCI, in performMulCombine() argument
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DAArch64ISelLowering.h252 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
523 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
526 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp392 TargetLowering::DAGCombinerInfo &DCI, in PerformADDECombine() argument
394 if (DCI.isBeforeLegalize()) in PerformADDECombine()
404 TargetLowering::DAGCombinerInfo &DCI, in PerformSUBECombine() argument
406 if (DCI.isBeforeLegalize()) in PerformSUBECombine()
416 TargetLowering::DAGCombinerInfo &DCI, in PerformDivRemCombine() argument
418 if (DCI.isBeforeLegalizeOps()) in PerformDivRemCombine()
526 TargetLowering::DAGCombinerInfo &DCI, in PerformSETCCCombine() argument
528 if (DCI.isBeforeLegalizeOps()) in PerformSETCCCombine()
543 TargetLowering::DAGCombinerInfo &DCI, in PerformANDCombine() argument
548 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) in PerformANDCombine()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1910 DAGCombinerInfo &DCI, DebugLoc dl) const { in SimplifySetCC() argument
1911 SelectionDAG &DAG = DCI.DAG; in SimplifySetCC()
1980 if (DCI.isBeforeLegalize() && N0->hasOneUse() && in SimplifySetCC()
2018 if (DCI.isBeforeLegalize() && in SimplifySetCC()
2110 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
2142 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
2143 DCI.AddToWorklist(ZextOp.getNode()); in SimplifySetCC()
2308 EVT ShiftTy = DCI.isBeforeLegalize() ? in SimplifySetCC()
2481 if (!DCI.isCalledByLegalizer()) in SimplifySetCC()
2482 DCI.AddToWorklist(SH.getNode()); in SimplifySetCC()
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/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp1373 TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUse() argument
1375 SelectionDAG &DAG = DCI.DAG; in combineSelectAndUse()
1397 combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, in combineSelectAndUseCommutative() argument
1402 if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes)) in combineSelectAndUseCommutative()
1405 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes)) in combineSelectAndUseCommutative()
1412 TargetLowering::DAGCombinerInfo &DCI) { in PerformSUBCombine() argument
1418 if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false)) in PerformSUBCombine()
1425 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
1432 return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false); in PerformDAGCombine()
1434 return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true); in PerformDAGCombine()
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DLanaiISelLowering.h106 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp3844 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombineWithOperands() argument
3847 SelectionDAG &DAG = DCI.DAG; in PerformADDCombineWithOperands()
3950 TargetLowering::DAGCombinerInfo &DCI, in PerformADDCombine() argument
3958 PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel)) in PerformADDCombine()
3962 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel); in PerformADDCombine()
3966 TargetLowering::DAGCombinerInfo &DCI) { in PerformANDCombine() argument
4028 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), in PerformANDCombine()
4034 DCI.CombineTo(N, Val, AddTo); in PerformANDCombine()
4041 TargetLowering::DAGCombinerInfo &DCI) { in PerformSELECTCombine() argument
4097 return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in PerformSELECTCombine()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp529 TargetLowering::DAGCombinerInfo &DCI, in performADDECombine() argument
531 if (DCI.isBeforeLegalize()) in performADDECombine()
549 TargetLowering::DAGCombinerInfo &DCI, in performANDCombine() argument
664 TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
784 TargetLowering::DAGCombinerInfo &DCI, in performSUBECombine() argument
786 if (DCI.isBeforeLegalize()) in performSUBECombine()
835 const TargetLowering::DAGCombinerInfo &DCI, in performMULCombine() argument
874 TargetLowering::DAGCombinerInfo &DCI, in performSHLCombine() argument
897 TargetLowering::DAGCombinerInfo &DCI, in performSRACombine() argument
943 TargetLowering::DAGCombinerInfo &DCI, in performSRLCombine() argument
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DMipsISelLowering.cpp467 TargetLowering::DAGCombinerInfo &DCI, in performDivRemCombine() argument
469 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
577 TargetLowering::DAGCombinerInfo &DCI, in performSELECTCombine() argument
579 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
656 TargetLowering::DAGCombinerInfo &DCI, in performCMovFPCombine() argument
658 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
683 TargetLowering::DAGCombinerInfo &DCI, in performANDCombine() argument
688 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
725 TargetLowering::DAGCombinerInfo &DCI, in performORCombine() argument
731 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
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DMipsSEISelLowering.h40 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp14919 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
14940 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRsqrtEstimate()
14946 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); in getRsqrtEstimate()
14952 DAGCombinerInfo &DCI, in getRecipEstimate() argument
14972 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals; in getRecipEstimate()
14977 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); in getRecipEstimate()
24673 TargetLowering::DAGCombinerInfo &DCI, in combineShuffle256() argument
24741 return DCI.CombineTo(N, InsV); in combineShuffle256()
25022 TargetLowering::DAGCombinerInfo &DCI, in combineX86ShuffleChain() argument
25039 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input), in combineX86ShuffleChain()
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DX86ISelLowering.h734 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
1223 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
1228 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1603 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
1604 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
1619 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1620 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1625 DCI.CommitTargetLoweringOpt(TLO); in PerformDAGCombine()
1636 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine()
1637 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1642 DCI.CommitTargetLoweringOpt(TLO); in PerformDAGCombine()
1800 if (!DCI.isBeforeLegalize() || in PerformDAGCombine()
1813 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); in PerformDAGCombine()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.h121 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;

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