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Searched refs:DREG (Results 1 – 8 of 8) sorted by relevance

/external/autotest/client/tests/unixbench/
DMakefile.patch50 ! cd $(SRCDIR); $(CC) -c ${CFLAGS} -DREG=register -DHZ=${HZ} ${OPTON} dhry_1.c
51 ! cd $(SRCDIR); $(CC) -c ${CFLAGS} -DREG=register -DHZ=${HZ} ${OPTON} dhry_2.c
61 ! cd $(SRCDIR); $(CC) -c ${CFLAGS} -DREG=register -DHZ=${HZ} ${OPTON} dhry_1.c -o dhry_1_reg.o
62 ! cd $(SRCDIR); $(CC) -c ${CFLAGS} -DREG=register -DHZ=${HZ} ${OPTON} dhry_2.c -o dhry_2_reg.o
/external/llvm/test/CodeGen/Thumb2/
D2013-03-02-vduplane-nonconstant-source-index.ll6 ; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[SOURCE]]:32]
7 ; CHECK: vst1.32 {[[DREG]], [[DREG2]]}, [r0]
/external/llvm/test/CodeGen/ARM/
Dfp16-v3.ll17 ; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]
18 ; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]
Dreg_sequence.ll276 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]]
/external/vixl/src/aarch64/
Doperands-aarch64.cc174 #define DREG(n) d##n, macro
175 const VRegister VRegister::dregisters[] = {AARCH64_REGISTER_CODE_LIST(DREG)};
176 #undef DREG
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dbitcast.ll87 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
88 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]]
Dfp.convert.ll140 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
141 ; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]+]], [[DREG]]
/external/llvm/lib/Target/AVR/
DAVRRegisterInfo.td87 // are printed as a `high:low` pair when a DREG is expected,