1; This tries to be a comprehensive test of f32 and f64 convert operations. 2; The CHECK lines are only checking for basic instruction patterns 3; that should be present regardless of the optimization level, so 4; there are no special OPTM1 match lines. 5 6; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s 7; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s 8 9; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \ 10; RUN: --target arm32 -i %s --args -O2 \ 11; RUN: | %if --need=target_ARM32 --command FileCheck %s \ 12; RUN: --check-prefix=ARM32 13 14; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \ 15; RUN: --target arm32 -i %s --args -Om1 \ 16; RUN: | %if --need=target_ARM32 --command FileCheck %s \ 17; RUN: --check-prefix=ARM32 18 19; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \ 20; RUN: --filetype=asm --target mips32 -i %s --args -Om1 \ 21; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \ 22; RUN: --check-prefix=MIPS32 23 24; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \ 25; RUN: --filetype=asm --target mips32 -i %s --args -O2 \ 26; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \ 27; RUN: --check-prefix=MIPS32O2 28 29define internal float @fptrunc(double %a) { 30entry: 31 %conv = fptrunc double %a to float 32 ret float %conv 33} 34; CHECK-LABEL: fptrunc 35; CHECK: cvtsd2ss 36; CHECK: fld 37; ARM32-LABEL: fptrunc 38; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}} 39; MIPS32-LABEL: fptrunc 40; MIPS32: cvt.s.d 41; MIPS32O2-LABEL: fptrunc 42; MIPS32O2: cvt.s.d 43 44define internal double @fpext(float %a) { 45entry: 46 %conv = fpext float %a to double 47 ret double %conv 48} 49; CHECK-LABEL: fpext 50; CHECK: cvtss2sd 51; CHECK: fld 52; ARM32-LABEL: fpext 53; ARM32: vcvt.f64.f32 {{d[0-9]+}}, {{s[0-9]+}} 54; MIPS32-LABEL: fpext 55; MIPS32: cvt.d.s 56; MIPS32O2-LABEL: fpext 57; MIPS32O2: cvt.d.s 58 59define internal i64 @doubleToSigned64(double %a) { 60entry: 61 %conv = fptosi double %a to i64 62 ret i64 %conv 63} 64; CHECK-LABEL: doubleToSigned64 65; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f64_i64 66; ARM32-LABEL: doubleToSigned64 67; TODO(jpp): implement this test. 68; MIPS32-LABEL: doubleToSigned64 69; MIPS32: jal __Sz_fptosi_f64_i64 70; MIPS32O2-LABEL: doubleToSigned64 71; MIPS32O2: jal __Sz_fptosi_f64_i64 72 73define internal i64 @floatToSigned64(float %a) { 74entry: 75 %conv = fptosi float %a to i64 76 ret i64 %conv 77} 78; CHECK-LABEL: floatToSigned64 79; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f32_i64 80; ARM32-LABEL: floatToSigned64 81; TODO(jpp): implement this test. 82; MIPS32-LABEL: floatToSigned64 83; MIPS32: jal __Sz_fptosi_f32_i64 84; MIPS32O2-LABEL: floatToSigned64 85; MIPS32O2: jal __Sz_fptosi_f32_i64 86 87define internal i64 @doubleToUnsigned64(double %a) { 88entry: 89 %conv = fptoui double %a to i64 90 ret i64 %conv 91} 92; CHECK-LABEL: doubleToUnsigned64 93; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i64 94; ARM32-LABEL: doubleToUnsigned64 95; TODO(jpp): implement this test. 96; MIPS32-LABEL: doubleToUnsigned64 97; MIPS32: jal __Sz_fptoui_f64_i64 98; MIPS32O2-LABEL: doubleToUnsigned64 99; MIPS32O2: jal __Sz_fptoui_f64_i64 100 101define internal i64 @floatToUnsigned64(float %a) { 102entry: 103 %conv = fptoui float %a to i64 104 ret i64 %conv 105} 106; CHECK-LABEL: floatToUnsigned64 107; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f32_i64 108; ARM32-LABEL: floatToUnsigned64 109; TODO(jpp): implement this test. 110; MIPS32-LABEL: floatToUnsigned64 111; MIPS32: jal __Sz_fptoui_f32_i64 112; MIPS32O2-LABEL: floatToUnsigned64 113; MIPS32O2: jal __Sz_fptoui_f32_i64 114 115define internal i32 @doubleToSigned32(double %a) { 116entry: 117 %conv = fptosi double %a to i32 118 ret i32 %conv 119} 120; CHECK-LABEL: doubleToSigned32 121; CHECK: cvttsd2si 122; ARM32-LABEL: doubleToSigned32 123; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} 124; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 125; MIPS32-LABEL: doubleToSigned32 126; MIPS32: trunc.w.d 127; MIPS32O2-LABEL: doubleToSigned32 128; MIPS32O2: trunc.w.d 129 130define internal i32 @doubleToSigned32Const() { 131entry: 132 %conv = fptosi double 867.5309 to i32 133 ret i32 %conv 134} 135; CHECK-LABEL: doubleToSigned32Const 136; CHECK: cvttsd2si 137; ARM32-LABEL: doubleToSigned32Const 138; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}} 139; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}} 140; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}} 141; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]+]], [[DREG]] 142; ARM32-DAF: vmov {{r[0-9]+}}, [[REG]] 143; MIPS32-LABEL: doubleToSigned32Const 144; MIPS32: lui 145; MIPS32: ldc1 146; MIPS32: trunc.w.d 147; MIPS32O2-LABEL: doubleToSigned32Const 148; MIPS32O2: lui 149; MIPS32O2: ldc1 150; MIPS32O2: trunc.w.d 151 152define internal i32 @floatToSigned32(float %a) { 153entry: 154 %conv = fptosi float %a to i32 155 ret i32 %conv 156} 157; CHECK-LABEL: floatToSigned32 158; CHECK: cvttss2si 159; ARM32-LABEL: floatToSigned32 160; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]+]], {{s[0-9]+}} 161; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 162; MIPS32-LABEL: floatToSigned32 163; MIPS32: trunc.w.s $f{{.*}}, $f{{.*}} 164; MIPS32O2-LABEL: floatToSigned32 165; MIPS32O2: trunc.w.s $[[REG:f[0-9]+]], $f{{.*}} 166; MIPS32O2: mfc1 $v0, $[[REG]] 167 168define internal i32 @doubleToUnsigned32(double %a) { 169entry: 170 %conv = fptoui double %a to i32 171 ret i32 %conv 172} 173; CHECK-LABEL: doubleToUnsigned32 174; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i32 175; ARM32-LABEL: doubleToUnsigned32 176; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]+]], {{d[0-9]+}} 177; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 178; MIPS32-LABEL: doubleToUnsigned32 179; MIPS32: jal __Sz_fptoui_f64_i32 180; MIPS32O2-LABEL: doubleToUnsigned32 181; MIPS32O2: jal __Sz_fptoui_f64_i32 182 183define internal i32 @floatToUnsigned32(float %a) { 184entry: 185 %conv = fptoui float %a to i32 186 ret i32 %conv 187} 188; CHECK-LABEL: floatToUnsigned32 189; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f32_i32 190; ARM32-LABEL: floatToUnsigned32 191; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]+]], {{s[0-9]+}} 192; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 193; MIPS32-LABEL: floatToUnsigned32 194; MIPS32: jal __Sz_fptoui_f32_i32 195; MIPS32O2-LABEL: floatToUnsigned32 196; MIPS32O2: jal __Sz_fptoui_f32_i32 197 198define internal i32 @doubleToSigned16(double %a) { 199entry: 200 %conv = fptosi double %a to i16 201 %conv.ret_ext = sext i16 %conv to i32 202 ret i32 %conv.ret_ext 203} 204; CHECK-LABEL: doubleToSigned16 205; CHECK: cvttsd2si 206; CHECK: movsx 207; ARM32-LABEL: doubleToSigned16 208; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} 209; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 210; ARM32: sxth 211; MIPS32-LABEL: doubleToSigned16 212; MIPS32: trunc.w.d 213; MIPS32O2-LABEL: doubleToSigned16 214; MIPS32O2: trunc.w.d 215 216define internal i32 @floatToSigned16(float %a) { 217entry: 218 %conv = fptosi float %a to i16 219 %conv.ret_ext = sext i16 %conv to i32 220 ret i32 %conv.ret_ext 221} 222; CHECK-LABEL: floatToSigned16 223; CHECK: cvttss2si 224; CHECK: movsx 225; ARM32-LABEL: floatToSigned16 226; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} 227; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 228; ARM32: sxth 229; MIPS32-LABEL: floatToSigned16 230; MIPS32: trunc.w.s 231; MIPS32O2-LABEL: floatToSigned16 232; MIPS32O2: trunc.w.s 233 234define internal i32 @doubleToUnsigned16(double %a) { 235entry: 236 %conv = fptoui double %a to i16 237 %conv.ret_ext = zext i16 %conv to i32 238 ret i32 %conv.ret_ext 239} 240; CHECK-LABEL: doubleToUnsigned16 241; CHECK: cvttsd2si 242; CHECK: movzx 243; ARM32-LABEL: doubleToUnsigned16 244; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} 245; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 246; ARM32: uxth 247; MIPS32-LABEL: doubleToUnsigned16 248; MIPS32: trunc.w.d 249; MIPS32O2-LABEL: doubleToUnsigned16 250; MIPS32O2: trunc.w.d 251 252define internal i32 @floatToUnsigned16(float %a) { 253entry: 254 %conv = fptoui float %a to i16 255 %conv.ret_ext = zext i16 %conv to i32 256 ret i32 %conv.ret_ext 257} 258; CHECK-LABEL: floatToUnsigned16 259; CHECK: cvttss2si 260; CHECK: movzx 261; ARM32-LABEL: floatToUnsigned16 262; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} 263; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 264; ARM32: uxth 265; MIPS32-LABEL: floatToUnsigned16 266; MIPS32: trunc.w.s 267; MIPS32O2-LABEL: floatToUnsigned16 268; MIPS32O2: trunc.w.s 269 270define internal i32 @doubleToSigned8(double %a) { 271entry: 272 %conv = fptosi double %a to i8 273 %conv.ret_ext = sext i8 %conv to i32 274 ret i32 %conv.ret_ext 275} 276; CHECK-LABEL: doubleToSigned8 277; CHECK: cvttsd2si 278; CHECK: movsx 279; ARM32-LABEL: doubleToSigned8 280; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} 281; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 282; ARM32: sxtb 283; MIPS32-LABEL: doubleToSigned8 284; MIPS32: trunc.w.d 285; MIPS32O2-LABEL: doubleToSigned8 286; MIPS32O2: trunc.w.d 287 288define internal i32 @floatToSigned8(float %a) { 289entry: 290 %conv = fptosi float %a to i8 291 %conv.ret_ext = sext i8 %conv to i32 292 ret i32 %conv.ret_ext 293} 294; CHECK-LABEL: floatToSigned8 295; CHECK: cvttss2si 296; CHECK: movsx 297; ARM32-LABEL: floatToSigned8 298; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} 299; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 300; ARM32: sxtb 301; MIPS32-LABEL: floatToSigned8 302; MIPS32: trunc.w.s 303; MIPS32O2-LABEL: floatToSigned8 304; MIPS32O2: trunc.w.s 305 306define internal i32 @doubleToUnsigned8(double %a) { 307entry: 308 %conv = fptoui double %a to i8 309 %conv.ret_ext = zext i8 %conv to i32 310 ret i32 %conv.ret_ext 311} 312; CHECK-LABEL: doubleToUnsigned8 313; CHECK: cvttsd2si 314; CHECK: movzx 315; ARM32-LABEL: doubleToUnsigned8 316; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} 317; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 318; ARM32: uxtb 319; MIPS32-LABEL: doubleToUnsigned8 320; MIPS32: trunc.w.d 321; MIPS32O2-LABEL: doubleToUnsigned8 322; MIPS32O2: trunc.w.d 323 324define internal i32 @floatToUnsigned8(float %a) { 325entry: 326 %conv = fptoui float %a to i8 327 %conv.ret_ext = zext i8 %conv to i32 328 ret i32 %conv.ret_ext 329} 330; CHECK-LABEL: floatToUnsigned8 331; CHECK: cvttss2si 332; CHECK: movzx 333; ARM32-LABEL: floatToUnsigned8 334; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} 335; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]] 336; ARM32: uxtb 337; MIPS32-LABEL: floatToUnsigned8 338; MIPS32: trunc.w.s 339; MIPS32O2-LABEL: floatToUnsigned8 340; MIPS32O2: trunc.w.s 341 342define internal i32 @doubleToUnsigned1(double %a) { 343entry: 344 %tobool = fptoui double %a to i1 345 %tobool.ret_ext = zext i1 %tobool to i32 346 ret i32 %tobool.ret_ext 347} 348; CHECK-LABEL: doubleToUnsigned1 349; CHECK: cvttsd2si 350; CHECK-NOT: and eax,0x1 351; ARM32-LABEL: doubleToUnsigned1 352; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} 353; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]] 354; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1 355; ARM32-NOT: uxth 356; ARM32-NOT: uxtb 357; MIPS32-LABEL: doubleToUnsigned1 358; MIPS32: trunc.w.d 359; MIPS32O2-LABEL: doubleToUnsigned1 360; MIPS32O2: trunc.w.d 361 362define internal i32 @floatToUnsigned1(float %a) { 363entry: 364 %tobool = fptoui float %a to i1 365 %tobool.ret_ext = zext i1 %tobool to i32 366 ret i32 %tobool.ret_ext 367} 368; CHECK-LABEL: floatToUnsigned1 369; CHECK: cvttss2si 370; CHECK-NOT: and eax,0x1 371; ARM32-LABEL: floatToUnsigned1 372; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} 373; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]] 374; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1 375; ARM32-NOT: uxth 376; ARM32-NOT: uxtb 377; MIPS32-LABEL: floatToUnsigned1 378; MIPS32: trunc.w.s 379; MIPS32O2-LABEL: floatToUnsigned1 380; MIPS32O2: trunc.w.s 381 382define internal double @signed64ToDouble(i64 %a) { 383entry: 384 %conv = sitofp i64 %a to double 385 ret double %conv 386} 387; CHECK-LABEL: signed64ToDouble 388; CHECK: call {{.*}} R_{{.*}} __Sz_sitofp_i64_f64 389; CHECK: fstp QWORD 390; ARM32-LABEL: signed64ToDouble 391; TODO(jpp): implement this test. 392; MIPS32-LABEL: signed64ToDouble 393; MIPS32: jal __Sz_sitofp_i64_f64 394; MIPS32O2-LABEL: signed64ToDouble 395; MIPS32O2: jal __Sz_sitofp_i64_f64 396 397define internal float @signed64ToFloat(i64 %a) { 398entry: 399 %conv = sitofp i64 %a to float 400 ret float %conv 401} 402; CHECK-LABEL: signed64ToFloat 403; CHECK: call {{.*}} R_{{.*}} __Sz_sitofp_i64_f32 404; CHECK: fstp DWORD 405; ARM32-LABEL: signed64ToFloat 406; TODO(jpp): implement this test. 407; MIPS32-LABEL: signed64ToFloat 408; MIPS32: jal __Sz_sitofp_i64_f32 409; MIPS32O2-LABEL: signed64ToFloat 410; MIPS32O2: jal __Sz_sitofp_i64_f32 411 412define internal double @unsigned64ToDouble(i64 %a) { 413entry: 414 %conv = uitofp i64 %a to double 415 ret double %conv 416} 417; CHECK-LABEL: unsigned64ToDouble 418; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i64_f64 419; CHECK: fstp 420; ARM32-LABEL: unsigned64ToDouble 421; TODO(jpp): implement this test. 422; MIPS32-LABEL: unsigned64ToDouble 423; MIPS32: jal __Sz_uitofp_i64_f64 424; MIPS32O2-LABEL: unsigned64ToDouble 425; MIPS32O2: jal __Sz_uitofp_i64_f64 426 427define internal float @unsigned64ToFloat(i64 %a) { 428entry: 429 %conv = uitofp i64 %a to float 430 ret float %conv 431} 432; CHECK-LABEL: unsigned64ToFloat 433; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i64_f32 434; CHECK: fstp 435; ARM32-LABEL: unsigned64ToFloat 436; TODO(jpp): implement this test. 437; MIPS32-LABEL: unsigned64ToFloat 438; MIPS32: jal __Sz_uitofp_i64_f32 439; MIPS32O2-LABEL: unsigned64ToFloat 440; MIPS32O2: jal __Sz_uitofp_i64_f32 441 442define internal double @unsigned64ToDoubleConst() { 443entry: 444 %conv = uitofp i64 12345678901234 to double 445 ret double %conv 446} 447; CHECK-LABEL: unsigned64ToDoubleConst 448; CHECK: mov DWORD PTR [esp+0x4],0xb3a 449; CHECK: mov DWORD PTR [esp],0x73ce2ff2 450; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i64_f64 451; CHECK: fstp 452; ARM32-LABEL: unsigned64ToDoubleConst 453; TODO(jpp): implement this test. 454; MIPS32-LABEL: unsigned64ToDoubleConst 455; MIPS32: jal __Sz_uitofp_i64_f64 456; MIPS32O2-LABEL: unsigned64ToDoubleConst 457; MIPS32O2: jal __Sz_uitofp_i64_f64 458 459define internal double @signed32ToDouble(i32 %a) { 460entry: 461 %conv = sitofp i32 %a to double 462 ret double %conv 463} 464; CHECK-LABEL: signed32ToDouble 465; CHECK: cvtsi2sd 466; CHECK: fld 467; ARM32-LABEL: signed32ToDouble 468; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}} 469; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]] 470; MIPS32-LABEL: signed32ToDouble 471; MIPS32: cvt.d.w 472; MIPS32O2-LABEL: signed32ToDouble 473; MIPS32O2: cvt.d.w 474 475define internal double @signed32ToDoubleConst() { 476entry: 477 %conv = sitofp i32 123 to double 478 ret double %conv 479} 480; CHECK-LABEL: signed32ToDoubleConst 481; CHECK: cvtsi2sd {{.*[^1]}} 482; CHECK: fld 483; ARM32-LABEL: signed32ToDoubleConst 484; ARM32-DAG: mov [[CONST:r[0-9]+]], #123 485; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[CONST]] 486; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]] 487; MIPS32-LABEL: signed32ToDoubleConst 488; MIPS32: cvt.d.w 489; MIPS32O2-LABEL: signed32ToDoubleConst 490; MIPS32O2: cvt.d.w 491 492define internal float @signed32ToFloat(i32 %a) { 493entry: 494 %conv = sitofp i32 %a to float 495 ret float %conv 496} 497; CHECK-LABEL: signed32ToFloat 498; CHECK: cvtsi2ss 499; CHECK: fld 500; ARM32-LABEL: signed32ToFloat 501; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}} 502; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]] 503; MIPS32-LABEL: signed32ToFloat 504; MIPS32: cvt.s.w $f{{.*}}, $f{{.*}} 505; MIPS32O2-LABEL: signed32ToFloat 506; MIPS32O2: mtc1 $a0, $[[REG:f[0-9]+]] 507; MIPS32O2: cvt.s.w $f{{.*}}, $[[REG]] 508 509define internal double @unsigned32ToDouble(i32 %a) { 510entry: 511 %conv = uitofp i32 %a to double 512 ret double %conv 513} 514; CHECK-LABEL: unsigned32ToDouble 515; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f64 516; CHECK: fstp QWORD 517; ARM32-LABEL: unsigned32ToDouble 518; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}} 519; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]] 520; MIPS32-LABEL: unsigned32ToDouble 521; MIPS32: jal __Sz_uitofp_i32_f64 522; MIPS32O2-LABEL: unsigned32ToDouble 523; MIPS32O2: jal __Sz_uitofp_i32_f64 524 525define internal float @unsigned32ToFloat(i32 %a) { 526entry: 527 %conv = uitofp i32 %a to float 528 ret float %conv 529} 530; CHECK-LABEL: unsigned32ToFloat 531; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f32 532; CHECK: fstp DWORD 533; ARM32-LABEL: unsigned32ToFloat 534; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}} 535; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]] 536; MIPS32-LABEL: unsigned32ToFloat 537; MIPS32: jal __Sz_uitofp_i32_f32 538; MIPS32O2-LABEL: unsigned32ToFloat 539; MIPS32O2: jal __Sz_uitofp_i32_f32 540 541define internal double @signed16ToDouble(i32 %a) { 542entry: 543 %a.arg_trunc = trunc i32 %a to i16 544 %conv = sitofp i16 %a.arg_trunc to double 545 ret double %conv 546} 547; CHECK-LABEL: signed16ToDouble 548; CHECK: cvtsi2sd 549; CHECK: fld QWORD 550; ARM32-LABEL: signed16ToDouble 551; ARM32-DAG: sxth [[INT:r[0-9]+]] 552; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 553; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]] 554; MIPS32-LABEL: signed16ToDouble 555; MIPS32: cvt.d.w 556; MIPS32O2-LABEL: signed16ToDouble 557; MIPS32O2: cvt.d.w 558 559define internal float @signed16ToFloat(i32 %a) { 560entry: 561 %a.arg_trunc = trunc i32 %a to i16 562 %conv = sitofp i16 %a.arg_trunc to float 563 ret float %conv 564} 565; CHECK-LABEL: signed16ToFloat 566; CHECK: cvtsi2ss 567; CHECK: fld DWORD 568; ARM32-LABEL: signed16ToFloat 569; ARM32-DAG: sxth [[INT:r[0-9]+]] 570; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 571; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]] 572; MIPS32-LABEL: signed16ToFloat 573; MIPS32: cvt.s.w 574; MIPS32O2-LABEL: signed16ToFloat 575; MIPS32O2: cvt.s.w 576 577define internal double @unsigned16ToDouble(i32 %a) { 578entry: 579 %a.arg_trunc = trunc i32 %a to i16 580 %conv = uitofp i16 %a.arg_trunc to double 581 ret double %conv 582} 583; CHECK-LABEL: unsigned16ToDouble 584; CHECK: cvtsi2sd 585; CHECK: fld 586; ARM32-LABEL: unsigned16ToDouble 587; ARM32-DAG: uxth [[INT:r[0-9]+]] 588; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 589; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]] 590; MIPS32-LABEL: unsigned16ToDouble 591; MIPS32: cvt.d.w 592; MIPS32O2-LABEL: unsigned16ToDouble 593; MIPS32O2: cvt.d.w 594 595define internal double @unsigned16ToDoubleConst() { 596entry: 597 %conv = uitofp i16 12345 to double 598 ret double %conv 599} 600; CHECK-LABEL: unsigned16ToDoubleConst 601; CHECK: cvtsi2sd 602; CHECK: fld 603; ARM32-LABEL: unsigned16ToDoubleConst 604; ARM32-DAG: movw [[INT:r[0-9]+]], #12345 605; ARM32-DAG: uxth [[INT]] 606; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 607; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]] 608; MIPS32-LABEL: unsigned16ToDoubleConst 609; MIPS32: cvt.d.w 610; MIPS32O2-LABEL: unsigned16ToDoubleConst 611; MIPS32O2: cvt.d.w 612 613define internal float @unsigned16ToFloat(i32 %a) { 614entry: 615 %a.arg_trunc = trunc i32 %a to i16 616 %conv = uitofp i16 %a.arg_trunc to float 617 ret float %conv 618} 619; CHECK-LABEL: unsigned16ToFloat 620; CHECK: cvtsi2ss 621; CHECK: fld 622; ARM32-LABEL: unsigned16ToFloat 623; ARM32-DAG: uxth [[INT:r[0-9]+]] 624; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 625; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]] 626; MIPS32-LABEL: unsigned16ToFloat 627; MIPS32: cvt.s.w 628; MIPS32O2-LABEL: unsigned16ToFloat 629; MIPS32O2: cvt.s.w 630 631define internal double @signed8ToDouble(i32 %a) { 632entry: 633 %a.arg_trunc = trunc i32 %a to i8 634 %conv = sitofp i8 %a.arg_trunc to double 635 ret double %conv 636} 637; CHECK-LABEL: signed8ToDouble 638; CHECK: cvtsi2sd 639; CHECK: fld 640; ARM32-LABEL: signed8ToDouble 641; ARM32-DAG: sxtb [[INT:r[0-9]+]] 642; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 643; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]] 644; MIPS32-LABEL: signed8ToDouble 645; MIPS32: cvt.d.w 646; MIPS32O2-LABEL: signed8ToDouble 647; MIPS32O2: cvt.d.w 648 649define internal float @signed8ToFloat(i32 %a) { 650entry: 651 %a.arg_trunc = trunc i32 %a to i8 652 %conv = sitofp i8 %a.arg_trunc to float 653 ret float %conv 654} 655; CHECK-LABEL: signed8ToFloat 656; CHECK: cvtsi2ss 657; CHECK: fld 658; ARM32-LABEL: signed8ToFloat 659; ARM32-DAG: sxtb [[INT:r[0-9]+]] 660; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 661; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]] 662; MIPS32-LABEL: signed8ToFloat 663; MIPS32: cvt.s.w 664; MIPS32O2-LABEL: signed8ToFloat 665; MIPS32O2: cvt.s.w 666 667define internal double @unsigned8ToDouble(i32 %a) { 668entry: 669 %a.arg_trunc = trunc i32 %a to i8 670 %conv = uitofp i8 %a.arg_trunc to double 671 ret double %conv 672} 673; CHECK-LABEL: unsigned8ToDouble 674; CHECK: cvtsi2sd 675; CHECK: fld 676; ARM32-LABEL: unsigned8ToDouble 677; ARM32-DAG: uxtb [[INT:r[0-9]+]] 678; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 679; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]] 680; MIPS32-LABEL: unsigned8ToDouble 681; MIPS32: cvt.d.w 682; MIPS32O2-LABEL: unsigned8ToDouble 683; MIPS32O2: cvt.d.w 684 685define internal float @unsigned8ToFloat(i32 %a) { 686entry: 687 %a.arg_trunc = trunc i32 %a to i8 688 %conv = uitofp i8 %a.arg_trunc to float 689 ret float %conv 690} 691; CHECK-LABEL: unsigned8ToFloat 692; CHECK: cvtsi2ss 693; CHECK: fld 694; ARM32-LABEL: unsigned8ToFloat 695; ARM32-DAG: uxtb [[INT:r[0-9]+]] 696; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 697; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]] 698; MIPS32-LABEL: unsigned8ToFloat 699; MIPS32: cvt.s.w 700; MIPS32O2-LABEL: unsigned8ToFloat 701; MIPS32O2: cvt.s.w 702 703define internal double @unsigned1ToDouble(i32 %a) { 704entry: 705 %a.arg_trunc = trunc i32 %a to i1 706 %conv = uitofp i1 %a.arg_trunc to double 707 ret double %conv 708} 709; CHECK-LABEL: unsigned1ToDouble 710; CHECK: cvtsi2sd 711; CHECK: fld 712; ARM32-LABEL: unsigned1ToDouble 713; ARM32-DAG: and [[INT:r[0-9]+]], {{r[0-9]+}}, #1 714; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 715; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]] 716; MIPS32-LABEL: unsigned1ToDouble 717; MIPS32: cvt.d.w 718; MIPS32O2-LABEL: unsigned1ToDouble 719; MIPS32O2: cvt.d.w 720 721define internal float @unsigned1ToFloat(i32 %a) { 722entry: 723 %a.arg_trunc = trunc i32 %a to i1 724 %conv = uitofp i1 %a.arg_trunc to float 725 ret float %conv 726} 727; CHECK-LABEL: unsigned1ToFloat 728; CHECK: cvtsi2ss 729; CHECK: fld 730; ARM32-LABEL: unsigned1ToFloat 731; ARM32-DAG: and [[INT:r[0-9]+]], {{r[0-9]+}}, #1 732; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]] 733; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]] 734; MIPS32-LABEL: unsigned1ToFloat 735; MIPS32: cvt.s.w 736; MIPS32O2-LABEL: unsigned1ToFloat 737; MIPS32O2: cvt.s.w 738 739define internal float @int32BitcastToFloat(i32 %a) { 740entry: 741 %conv = bitcast i32 %a to float 742 ret float %conv 743} 744; CHECK-LABEL: int32BitcastToFloat 745; CHECK: mov 746; ARM32-LABEL: int32BitcastToFloat 747; ARM32: vmov s{{[0-9]+}}, r{{[0-9]+}} 748; MIPS32-LABEL: int32BitcastToFloat 749; MIPS32: sw 750; MIPS32: lwc1 751; MIPS32O2-LABEL: int32BitcastToFloat 752 753define internal float @int32BitcastToFloatConst() { 754entry: 755 %conv = bitcast i32 8675309 to float 756 ret float %conv 757} 758; CHECK-LABEL: int32BitcastToFloatConst 759; CHECK: mov 760; ARM32-LABEL: int32BitcastToFloatConst 761; ARM32-DAG: movw [[REG:r[0-9]+]], #24557 762; ARM32-DAG: movt [[REG]], #132 763; ARM32: vmov s{{[0-9]+}}, [[REG]] 764; MIPS32-LABEL: int32BitcastToFloatConst 765; MIPS32: lwc1 766; MIPS32O2-LABEL: int32BitcastToFloatConst 767 768define internal double @int64BitcastToDouble(i64 %a) { 769entry: 770 %conv = bitcast i64 %a to double 771 ret double %conv 772} 773; CHECK-LABEL: int64BitcastToDouble 774; CHECK: mov 775; ARM32-LABEL: int64BitcastToDouble 776; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} 777; MIPS32-LABEL: int64BitcastToDouble 778; MIPS32: sw 779; MIPS32: sw 780; MIPS32: ldc1 781; MIPS32O2-LABEL: int64BitcastToDouble 782 783define internal double @int64BitcastToDoubleConst() { 784entry: 785 %conv = bitcast i64 9035768 to double 786 ret double %conv 787} 788; CHECK-LABEL: int64BitcastToDoubleConst 789; CHECK: mov 790; ARM32-LABEL: int64BitcastToDoubleConst 791; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 792; ARM32-DAG: movt [[REG0]], #137 793; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 794; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] 795; MIPS32-LABEL: int64BitcastToDoubleConst 796; MIPS32: ldc1 797; MIPS32O2-LABEL: int64BitcastToDoubleConst 798