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Searched refs:DefMI (Results 1 – 25 of 67) sorted by relevance

123

/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp95 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
97 if (DefMI->getParent() != MBB) in getAccDefMI()
99 if (DefMI->isCopyLike()) { in getAccDefMI()
100 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
102 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
106 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
108 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
114 return DefMI; in getAccDefMI()
149 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local
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DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
45 MachineInstr *DefMI = LastMI; in getHazardType() local
58 DefMI = &*I; in getHazardType()
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
64 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp155 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
159 return TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
164 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, in computeOperandLatency()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); in computeOperandLatency()
183 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI)); in computeOperandLatency()
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
211 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() in computeOperandLatency()
212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
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DLiveRangeEdit.cpp52 const MachineInstr *DefMI, in checkRematerializable() argument
54 assert(DefMI && "Missing instruction"); in checkRematerializable()
56 if (!TII.isTriviallyReMaterializable(*DefMI, aa)) in checkRematerializable()
69 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable() local
70 if (!DefMI) in scanRemattable()
72 checkRematerializable(OrigVNI, DefMI, aa); in scanRemattable()
166 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
172 if (DefMI && DefMI != MI) in foldAsLoad()
176 DefMI = MI; in foldAsLoad()
186 if (!DefMI || !UseMI) in foldAsLoad()
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DMachineTraceMetrics.cpp606 const MachineInstr *DefMI; member
610 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
611 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
619 DefMI = DefI->getParent(); in DataDep()
765 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local
767 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath()
770 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
838 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in computeInstrDepths()
843 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in computeInstrDepths()
845 if (!Dep.DefMI->isTransient()) in computeInstrDepths()
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DRegisterCoalescer.cpp664 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local
665 if (!DefMI) in removeCopyByCommutingDef()
667 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
671 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in removeCopyByCommutingDef()
674 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
687 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx)) in removeCopyByCommutingDef()
690 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef()
715 << *DefMI); in removeCopyByCommutingDef()
719 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef()
721 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx); in removeCopyByCommutingDef()
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DTargetInstrInfo.cpp1029 const MachineInstr &DefMI) const { in defaultDefLatency()
1030 if (DefMI.isTransient()) in defaultDefLatency()
1032 if (DefMI.mayLoad()) in defaultDefLatency()
1034 if (isHighLatencyDef(DefMI.getOpcode())) in defaultDefLatency()
1055 const MachineInstr &DefMI, in hasLowDefLatency() argument
1061 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1069 const MachineInstr &DefMI, in getOperandLatency() argument
1073 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1081 const InstrItineraryData *ItinData, const MachineInstr &DefMI) const { in computeDefOperandLatency()
1085 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency()
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DPHIElimination.cpp158 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
159 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
162 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
163 DefMI->eraseFromParent(); in runOnMachineFunction()
394 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
395 if (DefMI->isImplicitDef()) in LowerPHINode()
396 ImpDefs.insert(DefMI); in LowerPHINode()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveRangeEdit.cpp45 const MachineInstr *DefMI, in checkRematerializable() argument
48 assert(DefMI && "Missing instruction"); in checkRematerializable()
50 if (!tii.isTriviallyReMaterializable(DefMI, aa)) in checkRematerializable()
64 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def); in scanRemattable() local
65 if (!DefMI) in scanRemattable()
67 checkRematerializable(VNI, DefMI, tii, aa); in scanRemattable()
167 MachineInstr *DefMI = 0, *UseMI = 0; in foldAsLoad() local
175 if (DefMI && DefMI != MI) in foldAsLoad()
179 DefMI = MI; in foldAsLoad()
189 if (!DefMI || !UseMI) in foldAsLoad()
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DPHIElimination.cpp134 MachineInstr *DefMI = *I; in runOnMachineFunction() local
135 unsigned DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
137 DefMI->eraseFromParent(); in runOnMachineFunction()
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in isSourceDefinedByImplicitDef() local
177 if (!DefMI || !DefMI->isImplicitDef()) in isSourceDefinedByImplicitDef()
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in LowerAtomicPHINode() local
298 if (DefMI->isImplicitDef()) { in LowerAtomicPHINode()
299 ImpDefs.insert(DefMI); in LowerAtomicPHINode()
DTwoAddressInstructionPass.cpp91 MachineInstr *MI, MachineInstr *DefMI,
308 MachineInstr *MI, MachineInstr *DefMI, in isProfitableToReMat() argument
334 return MBB == DefMI->getParent(); in isProfitableToReMat()
429 MachineInstr *DefMI = &MI; in isKilled() local
431 if (!DefMI->killsRegister(Reg)) in isKilled()
440 DefMI = &*Begin; in isKilled()
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
1176 MachineInstr *DefMI = MRI->getVRegDef(regB); in runOnMachineFunction() local
1179 if (DefMI && in runOnMachineFunction()
1180 DefMI->getDesc().isAsCheapAsAMove() && in runOnMachineFunction()
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DInlineSpiller.cpp108 MachineInstr *DefMI; member
119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} in SibValueInfo()
122 bool hasDef() const { return DefByOrigPHI || DefMI; } in hasDef()
331 if (SVI.DefMI) in operator <<()
332 OS << " def: " << *SVI.DefMI; in operator <<()
395 DepSV.DefMI = SV.DefMI; in propagateSiblingValue()
484 return SVI->second.DefMI; in traceSiblingValue()
602 SVI->second.DefMI = MI; in traceSiblingValue()
623 return SVI->second.DefMI; in traceSiblingValue()
646 MachineInstr *DefMI = 0; in analyzeSiblingValues() local
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DRegisterCoalescer.cpp170 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
651 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in RemoveCopyByCommutingDef() local
652 if (!DefMI) in RemoveCopyByCommutingDef()
654 const MCInstrDesc &MCID = DefMI->getDesc(); in RemoveCopyByCommutingDef()
659 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); in RemoveCopyByCommutingDef()
662 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in RemoveCopyByCommutingDef()
665 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) in RemoveCopyByCommutingDef()
674 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in RemoveCopyByCommutingDef()
707 << *DefMI); in RemoveCopyByCommutingDef()
711 MachineBasicBlock *MBB = DefMI->getParent(); in RemoveCopyByCommutingDef()
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DMachineCSE.cpp125 MachineInstr *DefMI = MRI->getVRegDef(Reg); in PerformTrivialCoalescing() local
126 if (DefMI->getParent() != MBB) in PerformTrivialCoalescing()
128 if (!DefMI->isCopy()) in PerformTrivialCoalescing()
130 unsigned SrcReg = DefMI->getOperand(1).getReg(); in PerformTrivialCoalescing()
133 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) in PerformTrivialCoalescing()
137 DEBUG(dbgs() << "Coalescing: " << *DefMI); in PerformTrivialCoalescing()
141 DefMI->eraseFromParent(); in PerformTrivialCoalescing()
DPeepholeOptimizer.cpp294 MachineInstr *DefMI = MRI->getVRegDef(Src); in OptimizeBitcastInstr() local
295 if (!DefMI || !DefMI->getDesc().isBitcast()) in OptimizeBitcastInstr()
299 NumDefs = DefMI->getDesc().getNumDefs(); in OptimizeBitcastInstr()
300 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; in OptimizeBitcastInstr()
304 const MachineOperand &MO = DefMI->getOperand(i); in OptimizeBitcastInstr()
/external/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp126 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() local
130 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
131 unsigned FeedImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
133 = lookThruCopyLike(DefMI->getOperand(1).getReg()); in simplifyCode()
135 = lookThruCopyLike(DefMI->getOperand(2).getReg()); in simplifyCode()
156 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
157 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
169 .addOperand(DefMI->getOperand(1)); in simplifyCode()
DPPCVSXSwapRemoval.cpp614 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
615 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
617 int DefIdx = SwapMap[DefMI]; in formWebs()
624 DEBUG(DefMI->dump()); in formWebs()
694 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
695 unsigned DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
696 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
706 DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
724 DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
770 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval() local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DMLxExpansionPass.cpp92 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
94 if (DefMI->getParent() != MBB) in getAccDefMI()
96 if (DefMI->isCopyLike()) { in getAccDefMI()
97 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
99 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
102 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
103 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
105 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
111 return DefMI; in getAccDefMI()
160 MachineInstr *DefMI = getAccDefMI(MI); in FindMLxHazard() local
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DARMHazardRecognizer.cpp19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
48 MachineInstr *DefMI = LastMI; in getHazardType() local
58 DefMI = &*I; in getHazardType()
62 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
64 hasRAWHazard(DefMI, MI, TRI))) { in getHazardType()
/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp317 for (auto DefMI : List) { in chooseBestLEA() local
319 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1); in chooseBestLEA()
331 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
338 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
348 BestLEA = DefMI; in chooseBestLEA()
487 MachineInstr *DefMI; in removeRedundantAddrCalc() local
490 if (!chooseBestLEA(LEAs[getMemOpKey(MI, MemOpNo)], MI, DefMI, AddrDispShift, in removeRedundantAddrCalc()
501 DefMI->removeFromParent(); in removeRedundantAddrCalc()
502 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
503 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
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DX86CallFrameOptimization.cpp570 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
574 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
575 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
576 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
581 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
585 return &DefMI; in canFoldIntoRegPush()
/external/llvm/lib/Target/Mips/
DMipsOptimizePICCall.cpp261 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
263 assert(DefMI); in isCallViaRegister()
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
276 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
277 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
279 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp66 const MachineInstr *DefMI, unsigned DefIdx, in getOperandLatency() argument
71 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
114 const MachineInstr *DefMI, in hasLowDefLatency() argument
119 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp501 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI, this); in optimizeSelect() local
502 bool Invert = !DefMI; in optimizeSelect()
503 if (!DefMI) in optimizeSelect()
504 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI, this); in optimizeSelect()
505 if (!DefMI) in optimizeSelect()
517 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
520 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
523 NewMI.addOperand(DefMI->getOperand(i)); in optimizeSelect()
541 SeenMIs.erase(DefMI); in optimizeSelect()
547 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
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/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1190 MachineInstr *&DefMI) const { in optimizeLoadInstr() argument
1200 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
1233 const MachineInstr &DefMI, unsigned DefIdx,
1249 const MachineInstr &DefMI, unsigned DefIdx,
1267 const MachineInstr &DefMI) const;
1270 const MachineInstr &DefMI) const;
1282 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1291 const MachineInstr &DefMI,

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