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Searched refs:DstVT (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DFastISel.cpp666 EVT DstVT = TLI.getValueType(I->getType()); in SelectCast() local
669 DstVT == MVT::Other || !DstVT.isSimple()) in SelectCast()
674 if (!TLI.isTypeLegal(DstVT)) in SelectCast()
689 DstVT.getSimpleVT(), in SelectCast()
711 EVT DstVT = TLI.getValueType(I->getType()); in SelectBitCast() local
714 DstVT == MVT::Other || !DstVT.isSimple() || in SelectBitCast()
715 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) in SelectBitCast()
728 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { in SelectBitCast()
730 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); in SelectBitCast()
741 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in SelectBitCast()
[all …]
DLegalizeIntegerTypes.cpp2641 EVT DstVT = N->getValueType(0); in ExpandIntOp_SINT_TO_FP() local
2642 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); in ExpandIntOp_SINT_TO_FP()
2645 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); in ExpandIntOp_SINT_TO_FP()
2755 EVT DstVT = N->getValueType(0); in ExpandIntOp_UINT_TO_FP() local
2761 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT); in ExpandIntOp_UINT_TO_FP()
2765 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
2811 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), in ExpandIntOp_UINT_TO_FP()
2816 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); in ExpandIntOp_UINT_TO_FP()
2820 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP()
2823 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); in ExpandIntOp_UINT_TO_FP()
/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp279 void DecodeSubVectorBroadcast(MVT DstVT, MVT SrcVT, in DecodeSubVectorBroadcast() argument
281 assert(SrcVT.getScalarType() == DstVT.getScalarType() && in DecodeSubVectorBroadcast()
284 unsigned Scale = DstVT.getSizeInBits() / SrcVT.getSizeInBits(); in DecodeSubVectorBroadcast()
408 void DecodeZeroExtendMask(MVT SrcScalarVT, MVT DstVT, SmallVectorImpl<int> &Mask) { in DecodeZeroExtendMask() argument
409 unsigned NumDstElts = DstVT.getVectorNumElements(); in DecodeZeroExtendMask()
411 unsigned DstScalarBits = DstVT.getScalarSizeInBits(); in DecodeZeroExtendMask()
DX86ShuffleDecode.h92 void DecodeSubVectorBroadcast(MVT DstVT, MVT SrcVT,
122 void DecodeZeroExtendMask(MVT SrcScalarVT, MVT DstVT,
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
310 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
313 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
755 EVT DstVT = VA.getValVT(); in X86SelectRet() local
757 if (SrcVT != DstVT) { in X86SelectRet()
764 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet()
774 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
972 EVT DstVT = TLI.getValueType(I->getType()); in X86SelectZExt() local
973 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
985 if (DstVT != MVT::i8) { in X86SelectZExt()
[all …]
DX86SelectionDAGInfo.cpp243 EVT DstVT = Dst.getValueType(); in EmitTargetCodeForMemcpy() local
247 DAG.getNode(ISD::ADD, dl, DstVT, Dst, in EmitTargetCodeForMemcpy()
248 DAG.getConstant(Offset, DstVT)), in EmitTargetCodeForMemcpy()
DX86ISelDAGToDAG.cpp478 EVT DstVT = N->getValueType(0); in PreprocessISelDAG() local
481 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
487 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
505 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. in PreprocessISelDAG()
507 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG()
517 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, in PreprocessISelDAG()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1271 bit HasFloatModifiers, ValueType DstVT> {
1290 !if(!eq(DstVT.Size, 1),
1302 !if(!eq(DstVT.Size, 1),
1317 class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
1319 !if(!eq(DstVT.Size, 1),
1328 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1329 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1341 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
1342 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1350 getAsm32<HasDst, NumSrcArgs, DstVT>.ret,
[all …]
/external/llvm/lib/Transforms/Scalar/
DScalarizer.cpp491 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); in visitBitCastInst() local
493 if (!DstVT || !SrcVT) in visitBitCastInst()
496 unsigned DstNumElems = DstVT->getNumElements(); in visitBitCastInst()
505 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst()
511 Type *MidTy = VectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst()
537 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
DCodeGenPrepare.cpp368 EVT DstVT = TLI.getValueType(CI->getType()); in OptimizeNoopCopyExpression() local
371 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
376 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
384 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
386 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
389 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()
/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp266 EVT DstVT = Dst.getValueType(); in EmitTargetCodeForMemcpy() local
270 DAG.getNode(ISD::ADD, dl, DstVT, Dst, in EmitTargetCodeForMemcpy()
272 DstVT)), in EmitTargetCodeForMemcpy()
DX86FastISel.cpp97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
695 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
698 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
1212 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1214 if (SrcVT != DstVT) { in X86SelectRet()
1221 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet()
1231 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1506 EVT DstVT = TLI.getValueType(DL, I->getType()); in X86SelectZExt() local
1507 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1525 if (DstVT == MVT::i64) { in X86SelectZExt()
[all …]
DX86ISelDAGToDAG.cpp595 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
598 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
606 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
624 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. in PreprocessISelDAG()
626 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG()
636 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, in PreprocessISelDAG()
DX86InstrAVX512.td4985 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4988 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4989 (ins DstVT.FRC:$src1, SrcRC:$src),
4993 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4994 (ins DstVT.FRC:$src1, x86memop:$src),
4999 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
5000 (ins DstVT.RC:$src1, SrcRC:$src2),
5002 [(set DstVT.RC:$dst,
5003 (OpNode (DstVT.VT DstVT.RC:$src1),
5007 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1000 MVT DstVT; in SelectIToFP() local
1002 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1005 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1033 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) in SelectIToFP()
1055 if (DstVT == MVT::f32) in SelectIToFP()
1109 MVT DstVT, SrcVT; in SelectFPToI() local
1111 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1114 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1118 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT()) in SelectFPToI()
1149 if (DstVT == MVT::i32) in SelectFPToI()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1247 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1249 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1250 !DstVT.isSimple()) in selectCast()
1255 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1269 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1297 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1305 if (SrcVT == DstVT) { in selectBitCast()
1307 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1654 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
[all …]
DLegalizeIntegerTypes.cpp3028 EVT DstVT = N->getValueType(0); in ExpandIntOp_SINT_TO_FP() local
3029 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); in ExpandIntOp_SINT_TO_FP()
3032 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, SDLoc(N)).first; in ExpandIntOp_SINT_TO_FP()
3133 EVT DstVT = N->getValueType(0); in ExpandIntOp_UINT_TO_FP() local
3139 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); in ExpandIntOp_UINT_TO_FP()
3143 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
3193 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr, in ExpandIntOp_UINT_TO_FP()
3196 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); in ExpandIntOp_UINT_TO_FP()
3200 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP()
3203 return TLI.makeLibCall(DAG, LC, DstVT, Op, true, dl).first; in ExpandIntOp_UINT_TO_FP()
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp315 auto DstVT = TLI->getValueType(DL, Dst); in getExtractWithExtendCost() local
321 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT)) in getExtractWithExtendCost()
326 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits()) in getExtractWithExtendCost()
341 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u) in getExtractWithExtendCost()
DAArch64ISelDAGToDAG.cpp1045 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1068 DstVT = MVT::i32; in tryIndexedLoad()
1072 if (DstVT == MVT::i64) in tryIndexedLoad()
1078 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1081 DstVT = MVT::i32; in tryIndexedLoad()
1085 if (DstVT == MVT::i64) in tryIndexedLoad()
1091 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1094 DstVT = MVT::i32; in tryIndexedLoad()
1113 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp189 bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
1328 MVT DstVT; in SelectSIToFP() local
1330 if (!isTypeLegal(Ty, DstVT)) in SelectSIToFP()
1350 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectSIToFP()
1362 MVT DstVT; in SelectFPToSI() local
1364 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToSI()
1384 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToSI()
1511 bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, in FastEmitExtend() argument
1513 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in FastEmitExtend()
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3552 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3554 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3609 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3612 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3617 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3620 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3625 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3627 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3629 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3631 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
DMipsFastISel.cpp1049 MVT DstVT, SrcVT; in selectFPToInt() local
1054 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1057 if (DstVT != MVT::i32) in selectFPToInt()
DMipsDSPInstrInfo.td1312 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1314 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1538 MVT DstVT; in SelectIToFP() local
1540 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1571 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1582 MVT DstVT; in SelectFPToI() local
1584 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1603 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp810 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
813 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
818 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
826 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
828 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
831 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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