Searched refs:ExitSU (Results 1 – 19 of 19) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 158 ExitSU.setInstr(ExitMI); in AddSchedBarrierDeps()
171 Uses[Reg].push_back(&ExitSU); in AddSchedBarrierDeps()
183 Uses[Reg].push_back(&ExitSU); in AddSchedBarrierDeps()
277 if (DefSU == &ExitSU) in BuildSchedGraph()
288 if (DefSU == &ExitSU) in BuildSchedGraph()
312 UseSU != &ExitSU) { in BuildSchedGraph()
374 ExitSU.addPred(SDep(SU, SDep::Order, Latency, in BuildSchedGraph()
512 if (!ExitSU.isPred(SU)) in BuildSchedGraph()
515 ExitSU.addPred(SDep(SU, SDep::Order, 0, in BuildSchedGraph()
652 else if (SU == &ExitSU) in getGraphNodeLabel()
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| D | ScheduleDAG.cpp | 39 EntrySU(), ExitSU() { in ScheduleDAG()
74 ExitSU = SUnit(); in Run()
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| D | PostRASchedulerList.cpp | 325 ExitSU = SUnit(); in Schedule()
562 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAG.cpp | 41 MRI(mf.getRegInfo()), EntrySU(), ExitSU() { in ScheduleDAG()
53 ExitSU = SUnit(); in clearDAG()
468 if (ExitSU) in InitDAGTopologicalSorting()
469 WorkList.push_back(ExitSU); in InitDAGTopologicalSorting()
639 : SUnits(sunits), ExitSU(exitsu) {} in ScheduleDAGTopologicalSort()
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| D | MachineScheduler.cpp | 534 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU); in canAddEdge()
538 if (SuccSU != &ExitSU) { in addEdge()
577 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in releaseSucc()
777 ExitSU.biasCriticalPath(); in findRootsAndBiasEdges()
802 releasePredecessors(&ExitSU); in initQueues()
1007 if (SU.isScheduled || &SU == &ExitSU) in updatePressureDiffs()
1044 if (!SU->isScheduled && SU != &ExitSU) { in updatePressureDiffs()
1229 if (SU == &ExitSU) in computeCyclicCriticalPath()
1519 SUnit &ExitSU = DAG->ExitSU; in apply() local
1520 MachineInstr *Branch = ExitSU.getInstr(); in apply()
[all …]
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| D | ScheduleDAGInstrs.cpp | 251 ExitSU.setInstr(ExitMI); in addSchedBarrierDeps()
264 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); in addSchedBarrierDeps()
266 addVRegUseDeps(&ExitSU, i); in addSchedBarrierDeps()
276 Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg)); in addSchedBarrierDeps()
343 if (DefSU == &ExitSU) in addPhysRegDeps()
998 ExitSU.addPred(Dep); in buildSchedGraph()
1382 else if (SU == &ExitSU) in getGraphNodeLabel()
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| D | PostRASchedulerList.cpp | 489 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
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| D | MachinePipeliner.cpp | 265 Topo(SUnits, &ExitSU) {} in SwingSchedulerDAG()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 585 SUnit ExitSU; // Special node for the region exit.
712 SUnit *ExitSU;
734 ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
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| D | MachineScheduler.h | 258 LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), in ScheduleDAGMI()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGList.cpp | 125 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) in ReleaseSucc()
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| D | ScheduleDAGFast.cpp | 525 ReleasePredecessors(&ExitSU, CurCycle); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1267 ReleasePredecessors(&ExitSU); in ListScheduleBottomUp()
1328 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { in ReleaseSucc()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGVLIW.cpp | 135 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) { in releaseSucc()
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| D | ScheduleDAGFast.cpp | 536 ReleasePredecessors(&ExitSU, CurCycle); in ListScheduleBottomUp()
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| D | ScheduleDAGRRList.cpp | 1489 ReleasePredecessors(&ExitSU); in ListScheduleBottomUp()
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| /external/llvm/test/CodeGen/X86/ |
| D | misched-new.ll | 58 ; Test that the DAG builder can handle an undef vreg on ExitSU.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineScheduler.h | 454 SUnit& getExitSU() { return ExitSU; }; in getExitSU()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ScheduleDAG.h | 498 SUnit ExitSU; // Special node for the region exit.
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