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Searched refs:NewOpc (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp418 unsigned NewOpc; in translateImmediate() local
421 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break; in translateImmediate()
422 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break; in translateImmediate()
423 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break; in translateImmediate()
424 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break; in translateImmediate()
425 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break; in translateImmediate()
426 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break; in translateImmediate()
427 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break; in translateImmediate()
428 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break; in translateImmediate()
429 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break; in translateImmediate()
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/external/capstone/arch/X86/
DX86Disassembler.c219 unsigned NewOpc = 0; in translateImmediate() local
223 case X86_CMPPDrmi: NewOpc = X86_CMPPDrmi_alt; break; in translateImmediate()
224 case X86_CMPPDrri: NewOpc = X86_CMPPDrri_alt; break; in translateImmediate()
225 case X86_CMPPSrmi: NewOpc = X86_CMPPSrmi_alt; break; in translateImmediate()
226 case X86_CMPPSrri: NewOpc = X86_CMPPSrri_alt; break; in translateImmediate()
227 case X86_CMPSDrm: NewOpc = X86_CMPSDrm_alt; break; in translateImmediate()
228 case X86_CMPSDrr: NewOpc = X86_CMPSDrr_alt; break; in translateImmediate()
229 case X86_CMPSSrm: NewOpc = X86_CMPSSrm_alt; break; in translateImmediate()
230 case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; in translateImmediate()
233 if (NewOpc != 0) { in translateImmediate()
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/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp427 unsigned NewOpc; in Lower() local
430 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break; in Lower()
431 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
432 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
433 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
434 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
435 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
436 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
437 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
438 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; in Lower()
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/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp397 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
414 switch (NewOpc) { in genInstrWithNewOpc()
416 NewOpc = Mips::BEQZC; in genInstrWithNewOpc()
419 NewOpc = Mips::BNEZC; in genInstrWithNewOpc()
422 NewOpc = Mips::BGEZC; in genInstrWithNewOpc()
425 NewOpc = Mips::BLTZC; in genInstrWithNewOpc()
430 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
436 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 || in genInstrWithNewOpc()
437 NewOpc == Mips::JIALC64) { in genInstrWithNewOpc()
439 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64) in genInstrWithNewOpc()
DMipsSEInstrInfo.h90 unsigned NewOpc) const;
DMipsSEISelLowering.h68 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
DMipsInstrInfo.h133 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp746 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
747 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
847 unsigned NewOpc = 0; in MergeBaseUpdateLoadStore() local
865 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
884 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
902 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
911 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
913 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
918 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
925 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
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DThumb2InstrInfo.cpp436 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
437 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
470 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
480 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
492 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
497 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
518 if (NewOpc != Opcode) in rewriteT2FrameIndex()
519 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
552 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1571 unsigned NewOpc = 0; in OptimizeThumb2Instructions() local
1578 NewOpc = ARM::tLEApcrel; in OptimizeThumb2Instructions()
1585 NewOpc = ARM::tLDRpci; in OptimizeThumb2Instructions()
1592 if (!NewOpc) in OptimizeThumb2Instructions()
1599 U.MI->setDesc(TII->get(NewOpc)); in OptimizeThumb2Instructions()
1619 unsigned NewOpc = 0; in OptimizeThumb2Branches() local
1625 NewOpc = ARM::tB; in OptimizeThumb2Branches()
1630 NewOpc = ARM::tBcc; in OptimizeThumb2Branches()
1636 if (NewOpc) { in OptimizeThumb2Branches()
1640 Br.MI->setDesc(TII->get(NewOpc)); in OptimizeThumb2Branches()
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DARMISelLowering.cpp2266 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local
2268 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
4628 unsigned NewOpc = 0; in LowerMUL() local
4633 NewOpc = ARMISD::VMULLs; in LowerMUL()
4638 NewOpc = ARMISD::VMULLu; in LowerMUL()
4643 NewOpc = ARMISD::VMULLs; in LowerMUL()
4646 NewOpc = ARMISD::VMULLu; in LowerMUL()
4650 NewOpc = ARMISD::VMULLu; in LowerMUL()
4655 if (!NewOpc) { in LowerMUL()
4674 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
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DThumb1RegisterInfo.cpp504 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
505 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
506 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1261 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
1361 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1363 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1365 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1369 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add); in MergeBaseUpdateLoadStore()
1371 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub); in MergeBaseUpdateLoadStore()
1386 BuildMI(MBB, MBBI, DL, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
1395 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
1396 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
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DThumb2InstrInfo.cpp504 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
505 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
538 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
548 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
560 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
565 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
592 if (NewOpc != Opcode) in rewriteT2FrameIndex()
593 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
626 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1846 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1853 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1860 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1867 if (!NewOpc) in optimizeThumb2Instructions()
1880 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1903 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1909 NewOpc = ARM::tB; in optimizeThumb2Branches()
1914 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1920 if (NewOpc) { in optimizeThumb2Branches()
1925 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
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DARMExpandPseudoInsts.cpp1097 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local
1098 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
1136 unsigned NewOpc; in ExpandMI() local
1138 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
1139 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
1140 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
1141 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
1144 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), in ExpandMI()
1380 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
1382 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
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DThumbRegisterInfo.cpp396 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
397 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
398 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
/external/llvm/lib/Target/Hexagon/
DHexagonRDFOpt.cpp210 unsigned OpNum, NewOpc; in rewrite() local
213 NewOpc = Hexagon::L2_loadri_io; in rewrite()
217 NewOpc = Hexagon::L2_loadrd_io; in rewrite()
221 NewOpc = Hexagon::V6_vL32b_ai; in rewrite()
225 NewOpc = Hexagon::S2_storeri_io; in rewrite()
229 NewOpc = Hexagon::S2_storerd_io; in rewrite()
233 NewOpc = Hexagon::V6_vS32b_ai; in rewrite()
259 MI->setDesc(HII.get(NewOpc)); in rewrite()
DHexagonGenPredicate.cpp368 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
370 if (NewOpc == 0) { in convertToPredForm()
373 NewOpc = Hexagon::C2_not; in convertToPredForm()
376 NewOpc = TargetOpcode::COPY; in convertToPredForm()
403 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R); in convertToPredForm()
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp323 unsigned NewOpc; in convertCalleeSaveRestoreToSPPrePostIncDec() local
329 NewOpc = AArch64::STPXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
332 NewOpc = AArch64::STPDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
335 NewOpc = AArch64::STRXpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
339 NewOpc = AArch64::STRDpre; in convertCalleeSaveRestoreToSPPrePostIncDec()
343 NewOpc = AArch64::LDPXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
346 NewOpc = AArch64::LDPDpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
349 NewOpc = AArch64::LDRXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
353 NewOpc = AArch64::LDRDpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
358 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc)); in convertCalleeSaveRestoreToSPPrePostIncDec()
DAArch64AdvSIMDScalarPass.cpp300 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
301 assert(OldOpc != NewOpc && "transform an instruction to itself?!"); in transformInstruction()
370 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst) in transformInstruction()
/external/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
255 assert(NewOpc != 0 && "Unknown merged node opcode"); in insertMergedInstruction()
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc)); in insertMergedInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp619 unsigned NewOpc = 0; in Select() local
633 NewOpc = SPU::AIr32; in Select()
638 NewOpc = SPU::Ar32; in Select()
871 NewOpc = SPU::Ar32; in Select()
877 NewOpc = SPU::AIr32; in Select()
893 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); in Select()
895 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops); in Select()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86MCInstLower.cpp218 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { in LowerSubReg32_Op0() argument
219 OutMI.setOpcode(NewOpc); in LowerSubReg32_Op0()
223 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { in LowerUnaryToTwoAddr() argument
224 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
DX86InstrInfo.cpp2674 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
2678 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; in foldMemoryOperandImpl()
2679 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; in foldMemoryOperandImpl()
2680 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; in foldMemoryOperandImpl()
2681 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; in foldMemoryOperandImpl()
2688 MI->setDesc(get(NewOpc)); in foldMemoryOperandImpl()
2736 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
2739 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; in foldMemoryOperandImpl()
2740 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; in foldMemoryOperandImpl()
2741 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; in foldMemoryOperandImpl()
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