Searched refs:Op1Reg (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FastISel.cpp | 880 unsigned Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
881 if (Op1Reg == 0) return false; in X86FastEmitCompare()
884 .addReg(Op1Reg); in X86FastEmitCompare()
1176 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1177 if (Op1Reg == 0) return false; in X86SelectShift()
1179 CReg).addReg(Op1Reg); in X86SelectShift()
1220 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectSelect() local
1221 if (Op1Reg == 0) return false; in X86SelectSelect()
1229 .addReg(Op1Reg).addReg(Op2Reg); in X86SelectSelect()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 218 unsigned Op1Reg, bool Op1IsKill);
222 unsigned Op1Reg, bool Op1IsKill);
226 unsigned Op1Reg, bool Op1IsKill);
3909 unsigned Op1Reg, bool Op1IsKill) { in emitLSL_rr() argument
3924 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSL_rr()
3927 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr()
4015 unsigned Op1Reg, bool Op1IsKill) { in emitLSR_rr() argument
4031 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask); in emitLSR_rr()
4034 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr()
4136 unsigned Op1Reg, bool Op1IsKill) { in emitASR_rr() argument
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1620 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1621 if (Op1Reg == 0) return false; in SelectSelect()
1666 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2); in SelectSelect()
1670 .addReg(Op1Reg) in SelectSelect()
1674 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1); in SelectSelect()
1677 .addReg(Op1Reg) in SelectSelect()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1399 unsigned Op1Reg = getRegForValue(Op1); in X86FastEmitCompare() local
1400 if (Op1Reg == 0) return false; in X86FastEmitCompare()
1403 .addReg(Op1Reg); in X86FastEmitCompare()
1751 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectShift() local
1752 if (Op1Reg == 0) return false; in X86SelectShift()
1754 CReg).addReg(Op1Reg); in X86SelectShift()
1860 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in X86SelectDivRem() local
1861 if (Op1Reg == 0) in X86SelectDivRem()
1897 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()
|
| D | X86ISelLowering.cpp | 23364 unsigned Op1Reg = MIIt->getOperand(1).getReg(); in EmitLoweredSelect() local
23371 std::swap(Op1Reg, Op2Reg); in EmitLoweredSelect()
23373 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end()) in EmitLoweredSelect()
23374 Op1Reg = RegRewriteTable[Op1Reg].first; in EmitLoweredSelect()
23381 .addReg(Op1Reg).addMBB(copy0MBB) in EmitLoweredSelect()
23385 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg); in EmitLoweredSelect()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1757 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in selectShift() local
1758 if (!Op1Reg) in selectShift()
1775 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 1402 unsigned Op1Reg = getRegForValue(I->getOperand(1)); in SelectSelect() local
1403 if (Op1Reg == 0) return false; in SelectSelect()
1413 .addReg(Op1Reg).addReg(Op2Reg) in SelectSelect()
|