| /external/llvm/test/CodeGen/AArch64/ |
| D | rotate.ll | 4 ;; select ROTL. Make sure if generates the basic ushr/shl.
|
| /external/llvm/test/CodeGen/ARM/ |
| D | rotate.ll | 4 ;; select ROTL. Make sure if generates the basic VSHL/VSHR.
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 178 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, in addIPMSequence() local
180 return ROTL; in addIPMSequence()
|
| D | SystemZISelDAGToDAG.cpp | 807 case ISD::ROTL: { in expandRxSBG()
1269 case ISD::ROTL: in Select()
|
| /external/boringssl/src/decrepit/cast/ |
| D | cast.c | 85 #define ROTL(a, n) (_lrotl(a, n)) macro
87 #define ROTL(a, n) ((((a) << (n)) | ((a) >> ((-(n))&31))) & 0xffffffffL) macro
94 t = ROTL(t, (key[n * 2 + 1])); \
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 39 defm ROTL : BinaryInt<rotl, "rotl">;
|
| /external/vboot_reference/firmware/2lib/ |
| D | 2sha256.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| D | 2sha512.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/avb/libavb/ |
| D | avb_sha256.c | 42 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| D | avb_sha512.c | 42 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/vboot_reference/firmware/lib/cryptolib/ |
| D | sha256.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| D | sha512.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 157 case ISD::ROTL: in LegalizeOp()
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 1218 X86_INTRINSIC_DATA(avx512_mask_prolv_d_128, INTR_TYPE_2OP_MASK, ISD::ROTL, 0),
1219 X86_INTRINSIC_DATA(avx512_mask_prolv_d_256, INTR_TYPE_2OP_MASK, ISD::ROTL, 0),
1220 X86_INTRINSIC_DATA(avx512_mask_prolv_d_512, INTR_TYPE_2OP_MASK, ISD::ROTL, 0),
1221 X86_INTRINSIC_DATA(avx512_mask_prolv_q_128, INTR_TYPE_2OP_MASK, ISD::ROTL, 0),
1222 X86_INTRINSIC_DATA(avx512_mask_prolv_q_256, INTR_TYPE_2OP_MASK, ISD::ROTL, 0),
1223 X86_INTRINSIC_DATA(avx512_mask_prolv_q_512, INTR_TYPE_2OP_MASK, ISD::ROTL, 0),
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 358 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
944 N->getOperand(0).getOpcode() != ISD::ROTL) { in Select()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 104 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
106 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 175 setOperationAction(ISD::ROTL, MVT::i64, Legal); in NVPTXTargetLowering()
178 setOperationAction(ISD::ROTL, MVT::i64, Expand); in NVPTXTargetLowering()
182 setOperationAction(ISD::ROTL, MVT::i32, Legal); in NVPTXTargetLowering()
185 setOperationAction(ISD::ROTL, MVT::i32, Expand); in NVPTXTargetLowering()
189 setOperationAction(ISD::ROTL, MVT::i16, Expand); in NVPTXTargetLowering()
191 setOperationAction(ISD::ROTL, MVT::i8, Expand); in NVPTXTargetLowering()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 194 case ISD::ROTL: return "rotl"; in getOperationName()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 239 setOperationAction(ISD::ROTL, MVT::i32, Legal); in SPUTargetLowering()
240 setOperationAction(ISD::ROTL, MVT::i16, Legal); in SPUTargetLowering()
241 setOperationAction(ISD::ROTL, MVT::i8, Custom); in SPUTargetLowering()
2225 case ISD::ROTL: { in LowerI8Math()
2810 case ISD::ROTL: in LowerOperation()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 97 setOperationAction(ISD::ROTL, MVT::i8, Expand); in MSP430TargetLowering()
99 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 96 setOperationAction(ISD::ROTL, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/mmc-utils/3rdparty/hmac_sha/ |
| D | sha2.c | 48 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) macro
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 496 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
921 case ISD::ROTL: in getValueBits()
1966 case ISD::ROTL: in tryBitPermutation()
2612 N->getOperand(0).getOpcode() != ISD::ROTL) { in Select()
|