1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "ppc-codegen"
16 #include "PPC.h"
17 #include "PPCTargetMachine.h"
18 #include "MCTargetDesc/PPCPredicates.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 using namespace llvm;
35
36 namespace {
37 //===--------------------------------------------------------------------===//
38 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
39 /// instructions for SelectionDAG operations.
40 ///
41 class PPCDAGToDAGISel : public SelectionDAGISel {
42 const PPCTargetMachine &TM;
43 const PPCTargetLowering &PPCLowering;
44 const PPCSubtarget &PPCSubTarget;
45 unsigned GlobalBaseReg;
46 public:
PPCDAGToDAGISel(PPCTargetMachine & tm)47 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
48 : SelectionDAGISel(tm), TM(tm),
49 PPCLowering(*TM.getTargetLowering()),
50 PPCSubTarget(*TM.getSubtargetImpl()) {}
51
runOnMachineFunction(MachineFunction & MF)52 virtual bool runOnMachineFunction(MachineFunction &MF) {
53 // Make sure we re-emit a set of the global base reg if necessary
54 GlobalBaseReg = 0;
55 SelectionDAGISel::runOnMachineFunction(MF);
56
57 InsertVRSaveCode(MF);
58 return true;
59 }
60
61 /// getI32Imm - Return a target constant with the specified value, of type
62 /// i32.
getI32Imm(unsigned Imm)63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
65 }
66
67 /// getI64Imm - Return a target constant with the specified value, of type
68 /// i64.
getI64Imm(uint64_t Imm)69 inline SDValue getI64Imm(uint64_t Imm) {
70 return CurDAG->getTargetConstant(Imm, MVT::i64);
71 }
72
73 /// getSmallIPtrImm - Return a target constant of pointer type.
getSmallIPtrImm(unsigned Imm)74 inline SDValue getSmallIPtrImm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
76 }
77
78 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
79 /// with any number of 0s on either side. The 1s are allowed to wrap from
80 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
81 /// 0x0F0F0000 is not, since all 1s are not contiguous.
82 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
83
84
85 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
86 /// rotate and mask opcode and mask operation.
87 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
88 unsigned &SH, unsigned &MB, unsigned &ME);
89
90 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
91 /// base register. Return the virtual register that holds this value.
92 SDNode *getGlobalBaseReg();
93
94 // Select - Convert the specified operand from a target-independent to a
95 // target-specific node if it hasn't already been changed.
96 SDNode *Select(SDNode *N);
97
98 SDNode *SelectBitfieldInsert(SDNode *N);
99
100 /// SelectCC - Select a comparison of the specified values with the
101 /// specified condition code, returning the CR# of the expression.
102 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
103
104 /// SelectAddrImm - Returns true if the address N can be represented by
105 /// a base register plus a signed 16-bit displacement [r+imm].
SelectAddrImm(SDValue N,SDValue & Disp,SDValue & Base)106 bool SelectAddrImm(SDValue N, SDValue &Disp,
107 SDValue &Base) {
108 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
109 }
110
111 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
112 /// immediate field. Because preinc imms have already been validated, just
113 /// accept it.
SelectAddrImmOffs(SDValue N,SDValue & Out) const114 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
115 Out = N;
116 return true;
117 }
118
119 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
120 /// represented as an indexed [r+r] operation. Returns false if it can
121 /// be represented by [r+imm], which are preferred.
SelectAddrIdx(SDValue N,SDValue & Base,SDValue & Index)122 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
123 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
124 }
125
126 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
127 /// represented as an indexed [r+r] operation.
SelectAddrIdxOnly(SDValue N,SDValue & Base,SDValue & Index)128 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
129 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
130 }
131
132 /// SelectAddrImmShift - Returns true if the address N can be represented by
133 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
134 /// for use by STD and friends.
SelectAddrImmShift(SDValue N,SDValue & Disp,SDValue & Base)135 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) {
136 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
137 }
138
139 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
140 /// inline asm expressions. It is always correct to compute the value into
141 /// a register. The case of adding a (possibly relocatable) constant to a
142 /// register can be improved, but it is wrong to substitute Reg+Reg for
143 /// Reg in an asm, because the load or store opcode would have to change.
SelectInlineAsmMemoryOperand(const SDValue & Op,char ConstraintCode,std::vector<SDValue> & OutOps)144 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
145 char ConstraintCode,
146 std::vector<SDValue> &OutOps) {
147 OutOps.push_back(Op);
148 return false;
149 }
150
151 void InsertVRSaveCode(MachineFunction &MF);
152
getPassName() const153 virtual const char *getPassName() const {
154 return "PowerPC DAG->DAG Pattern Instruction Selection";
155 }
156
157 // Include the pieces autogenerated from the target description.
158 #include "PPCGenDAGISel.inc"
159
160 private:
161 SDNode *SelectSETCC(SDNode *N);
162 };
163 }
164
165 /// InsertVRSaveCode - Once the entire function has been instruction selected,
166 /// all virtual registers are created and all machine instructions are built,
167 /// check to see if we need to save/restore VRSAVE. If so, do it.
InsertVRSaveCode(MachineFunction & Fn)168 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
169 // Check to see if this function uses vector registers, which means we have to
170 // save and restore the VRSAVE register and update it with the regs we use.
171 //
172 // In this case, there will be virtual registers of vector type created
173 // by the scheduler. Detect them now.
174 bool HasVectorVReg = false;
175 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
176 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
177 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
178 HasVectorVReg = true;
179 break;
180 }
181 }
182 if (!HasVectorVReg) return; // nothing to do.
183
184 // If we have a vector register, we want to emit code into the entry and exit
185 // blocks to save and restore the VRSAVE register. We do this here (instead
186 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
187 //
188 // 1. This (trivially) reduces the load on the register allocator, by not
189 // having to represent the live range of the VRSAVE register.
190 // 2. This (more significantly) allows us to create a temporary virtual
191 // register to hold the saved VRSAVE value, allowing this temporary to be
192 // register allocated, instead of forcing it to be spilled to the stack.
193
194 // Create two vregs - one to hold the VRSAVE register that is live-in to the
195 // function and one for the value after having bits or'd into it.
196 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
197 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
198
199 const TargetInstrInfo &TII = *TM.getInstrInfo();
200 MachineBasicBlock &EntryBB = *Fn.begin();
201 DebugLoc dl;
202 // Emit the following code into the entry block:
203 // InVRSAVE = MFVRSAVE
204 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
205 // MTVRSAVE UpdatedVRSAVE
206 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
207 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
208 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
209 UpdatedVRSAVE).addReg(InVRSAVE);
210 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
211
212 // Find all return blocks, outputting a restore in each epilog.
213 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
214 if (!BB->empty() && BB->back().getDesc().isReturn()) {
215 IP = BB->end(); --IP;
216
217 // Skip over all terminator instructions, which are part of the return
218 // sequence.
219 MachineBasicBlock::iterator I2 = IP;
220 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
221 IP = I2;
222
223 // Emit: MTVRSAVE InVRSave
224 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
225 }
226 }
227 }
228
229
230 /// getGlobalBaseReg - Output the instructions required to put the
231 /// base address to use for accessing globals into a register.
232 ///
getGlobalBaseReg()233 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
234 if (!GlobalBaseReg) {
235 const TargetInstrInfo &TII = *TM.getInstrInfo();
236 // Insert the set of GlobalBaseReg into the first MBB of the function
237 MachineBasicBlock &FirstMBB = MF->front();
238 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
239 DebugLoc dl;
240
241 if (PPCLowering.getPointerTy() == MVT::i32) {
242 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
243 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
244 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
245 } else {
246 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
247 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
248 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
249 }
250 }
251 return CurDAG->getRegister(GlobalBaseReg,
252 PPCLowering.getPointerTy()).getNode();
253 }
254
255 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
256 /// or 64-bit immediate, and if the value can be accurately represented as a
257 /// sign extension from a 16-bit value. If so, this returns true and the
258 /// immediate.
isIntS16Immediate(SDNode * N,short & Imm)259 static bool isIntS16Immediate(SDNode *N, short &Imm) {
260 if (N->getOpcode() != ISD::Constant)
261 return false;
262
263 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
264 if (N->getValueType(0) == MVT::i32)
265 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
266 else
267 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
268 }
269
isIntS16Immediate(SDValue Op,short & Imm)270 static bool isIntS16Immediate(SDValue Op, short &Imm) {
271 return isIntS16Immediate(Op.getNode(), Imm);
272 }
273
274
275 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
276 /// operand. If so Imm will receive the 32-bit value.
isInt32Immediate(SDNode * N,unsigned & Imm)277 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
278 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
279 Imm = cast<ConstantSDNode>(N)->getZExtValue();
280 return true;
281 }
282 return false;
283 }
284
285 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
286 /// operand. If so Imm will receive the 64-bit value.
isInt64Immediate(SDNode * N,uint64_t & Imm)287 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
288 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
289 Imm = cast<ConstantSDNode>(N)->getZExtValue();
290 return true;
291 }
292 return false;
293 }
294
295 // isInt32Immediate - This method tests to see if a constant operand.
296 // If so Imm will receive the 32 bit value.
isInt32Immediate(SDValue N,unsigned & Imm)297 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
298 return isInt32Immediate(N.getNode(), Imm);
299 }
300
301
302 // isOpcWithIntImmediate - This method tests to see if the node is a specific
303 // opcode and that it has a immediate integer right operand.
304 // If so Imm will receive the 32 bit value.
isOpcWithIntImmediate(SDNode * N,unsigned Opc,unsigned & Imm)305 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
306 return N->getOpcode() == Opc
307 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
308 }
309
isRunOfOnes(unsigned Val,unsigned & MB,unsigned & ME)310 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
311 if (isShiftedMask_32(Val)) {
312 // look for the first non-zero bit
313 MB = CountLeadingZeros_32(Val);
314 // look for the first zero bit after the run of ones
315 ME = CountLeadingZeros_32((Val - 1) ^ Val);
316 return true;
317 } else {
318 Val = ~Val; // invert mask
319 if (isShiftedMask_32(Val)) {
320 // effectively look for the first zero bit
321 ME = CountLeadingZeros_32(Val) - 1;
322 // effectively look for the first one bit after the run of zeros
323 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
324 return true;
325 }
326 }
327 // no run present
328 return false;
329 }
330
isRotateAndMask(SDNode * N,unsigned Mask,bool isShiftMask,unsigned & SH,unsigned & MB,unsigned & ME)331 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
332 bool isShiftMask, unsigned &SH,
333 unsigned &MB, unsigned &ME) {
334 // Don't even go down this path for i64, since different logic will be
335 // necessary for rldicl/rldicr/rldimi.
336 if (N->getValueType(0) != MVT::i32)
337 return false;
338
339 unsigned Shift = 32;
340 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
341 unsigned Opcode = N->getOpcode();
342 if (N->getNumOperands() != 2 ||
343 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
344 return false;
345
346 if (Opcode == ISD::SHL) {
347 // apply shift left to mask if it comes first
348 if (isShiftMask) Mask = Mask << Shift;
349 // determine which bits are made indeterminant by shift
350 Indeterminant = ~(0xFFFFFFFFu << Shift);
351 } else if (Opcode == ISD::SRL) {
352 // apply shift right to mask if it comes first
353 if (isShiftMask) Mask = Mask >> Shift;
354 // determine which bits are made indeterminant by shift
355 Indeterminant = ~(0xFFFFFFFFu >> Shift);
356 // adjust for the left rotate
357 Shift = 32 - Shift;
358 } else if (Opcode == ISD::ROTL) {
359 Indeterminant = 0;
360 } else {
361 return false;
362 }
363
364 // if the mask doesn't intersect any Indeterminant bits
365 if (Mask && !(Mask & Indeterminant)) {
366 SH = Shift & 31;
367 // make sure the mask is still a mask (wrap arounds may not be)
368 return isRunOfOnes(Mask, MB, ME);
369 }
370 return false;
371 }
372
373 /// SelectBitfieldInsert - turn an or of two masked values into
374 /// the rotate left word immediate then mask insert (rlwimi) instruction.
SelectBitfieldInsert(SDNode * N)375 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
376 SDValue Op0 = N->getOperand(0);
377 SDValue Op1 = N->getOperand(1);
378 DebugLoc dl = N->getDebugLoc();
379
380 APInt LKZ, LKO, RKZ, RKO;
381 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
382 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
383
384 unsigned TargetMask = LKZ.getZExtValue();
385 unsigned InsertMask = RKZ.getZExtValue();
386
387 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
388 unsigned Op0Opc = Op0.getOpcode();
389 unsigned Op1Opc = Op1.getOpcode();
390 unsigned Value, SH = 0;
391 TargetMask = ~TargetMask;
392 InsertMask = ~InsertMask;
393
394 // If the LHS has a foldable shift and the RHS does not, then swap it to the
395 // RHS so that we can fold the shift into the insert.
396 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
397 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
398 Op0.getOperand(0).getOpcode() == ISD::SRL) {
399 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
400 Op1.getOperand(0).getOpcode() != ISD::SRL) {
401 std::swap(Op0, Op1);
402 std::swap(Op0Opc, Op1Opc);
403 std::swap(TargetMask, InsertMask);
404 }
405 }
406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
407 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
408 Op1.getOperand(0).getOpcode() != ISD::SRL) {
409 std::swap(Op0, Op1);
410 std::swap(Op0Opc, Op1Opc);
411 std::swap(TargetMask, InsertMask);
412 }
413 }
414
415 unsigned MB, ME;
416 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
417 SDValue Tmp1, Tmp2;
418
419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
420 isInt32Immediate(Op1.getOperand(1), Value)) {
421 Op1 = Op1.getOperand(0);
422 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
423 }
424 if (Op1Opc == ISD::AND) {
425 unsigned SHOpc = Op1.getOperand(0).getOpcode();
426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
427 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
428 Op1 = Op1.getOperand(0).getOperand(0);
429 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
430 } else {
431 Op1 = Op1.getOperand(0);
432 }
433 }
434
435 SH &= 31;
436 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
437 getI32Imm(ME) };
438 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
439 }
440 }
441 return 0;
442 }
443
444 /// SelectCC - Select a comparison of the specified values with the specified
445 /// condition code, returning the CR# of the expression.
SelectCC(SDValue LHS,SDValue RHS,ISD::CondCode CC,DebugLoc dl)446 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
447 ISD::CondCode CC, DebugLoc dl) {
448 // Always select the LHS.
449 unsigned Opc;
450
451 if (LHS.getValueType() == MVT::i32) {
452 unsigned Imm;
453 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
454 if (isInt32Immediate(RHS, Imm)) {
455 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
456 if (isUInt<16>(Imm))
457 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
458 getI32Imm(Imm & 0xFFFF)), 0);
459 // If this is a 16-bit signed immediate, fold it.
460 if (isInt<16>((int)Imm))
461 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
462 getI32Imm(Imm & 0xFFFF)), 0);
463
464 // For non-equality comparisons, the default code would materialize the
465 // constant, then compare against it, like this:
466 // lis r2, 4660
467 // ori r2, r2, 22136
468 // cmpw cr0, r3, r2
469 // Since we are just comparing for equality, we can emit this instead:
470 // xoris r0,r3,0x1234
471 // cmplwi cr0,r0,0x5678
472 // beq cr0,L6
473 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
474 getI32Imm(Imm >> 16)), 0);
475 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
476 getI32Imm(Imm & 0xFFFF)), 0);
477 }
478 Opc = PPC::CMPLW;
479 } else if (ISD::isUnsignedIntSetCC(CC)) {
480 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
481 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
482 getI32Imm(Imm & 0xFFFF)), 0);
483 Opc = PPC::CMPLW;
484 } else {
485 short SImm;
486 if (isIntS16Immediate(RHS, SImm))
487 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
488 getI32Imm((int)SImm & 0xFFFF)),
489 0);
490 Opc = PPC::CMPW;
491 }
492 } else if (LHS.getValueType() == MVT::i64) {
493 uint64_t Imm;
494 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
495 if (isInt64Immediate(RHS.getNode(), Imm)) {
496 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
497 if (isUInt<16>(Imm))
498 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
499 getI32Imm(Imm & 0xFFFF)), 0);
500 // If this is a 16-bit signed immediate, fold it.
501 if (isInt<16>(Imm))
502 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
503 getI32Imm(Imm & 0xFFFF)), 0);
504
505 // For non-equality comparisons, the default code would materialize the
506 // constant, then compare against it, like this:
507 // lis r2, 4660
508 // ori r2, r2, 22136
509 // cmpd cr0, r3, r2
510 // Since we are just comparing for equality, we can emit this instead:
511 // xoris r0,r3,0x1234
512 // cmpldi cr0,r0,0x5678
513 // beq cr0,L6
514 if (isUInt<32>(Imm)) {
515 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
516 getI64Imm(Imm >> 16)), 0);
517 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
518 getI64Imm(Imm & 0xFFFF)), 0);
519 }
520 }
521 Opc = PPC::CMPLD;
522 } else if (ISD::isUnsignedIntSetCC(CC)) {
523 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
524 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
525 getI64Imm(Imm & 0xFFFF)), 0);
526 Opc = PPC::CMPLD;
527 } else {
528 short SImm;
529 if (isIntS16Immediate(RHS, SImm))
530 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
531 getI64Imm(SImm & 0xFFFF)),
532 0);
533 Opc = PPC::CMPD;
534 }
535 } else if (LHS.getValueType() == MVT::f32) {
536 Opc = PPC::FCMPUS;
537 } else {
538 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
539 Opc = PPC::FCMPUD;
540 }
541 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
542 }
543
getPredicateForSetCC(ISD::CondCode CC)544 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
545 switch (CC) {
546 case ISD::SETUEQ:
547 case ISD::SETONE:
548 case ISD::SETOLE:
549 case ISD::SETOGE:
550 llvm_unreachable("Should be lowered by legalize!");
551 default: llvm_unreachable("Unknown condition!");
552 case ISD::SETOEQ:
553 case ISD::SETEQ: return PPC::PRED_EQ;
554 case ISD::SETUNE:
555 case ISD::SETNE: return PPC::PRED_NE;
556 case ISD::SETOLT:
557 case ISD::SETLT: return PPC::PRED_LT;
558 case ISD::SETULE:
559 case ISD::SETLE: return PPC::PRED_LE;
560 case ISD::SETOGT:
561 case ISD::SETGT: return PPC::PRED_GT;
562 case ISD::SETUGE:
563 case ISD::SETGE: return PPC::PRED_GE;
564 case ISD::SETO: return PPC::PRED_NU;
565 case ISD::SETUO: return PPC::PRED_UN;
566 // These two are invalid for floating point. Assume we have int.
567 case ISD::SETULT: return PPC::PRED_LT;
568 case ISD::SETUGT: return PPC::PRED_GT;
569 }
570 }
571
572 /// getCRIdxForSetCC - Return the index of the condition register field
573 /// associated with the SetCC condition, and whether or not the field is
574 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
575 ///
576 /// If this returns with Other != -1, then the returned comparison is an or of
577 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
getCRIdxForSetCC(ISD::CondCode CC,bool & Invert,int & Other)578 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
579 Invert = false;
580 Other = -1;
581 switch (CC) {
582 default: llvm_unreachable("Unknown condition!");
583 case ISD::SETOLT:
584 case ISD::SETLT: return 0; // Bit #0 = SETOLT
585 case ISD::SETOGT:
586 case ISD::SETGT: return 1; // Bit #1 = SETOGT
587 case ISD::SETOEQ:
588 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
589 case ISD::SETUO: return 3; // Bit #3 = SETUO
590 case ISD::SETUGE:
591 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
592 case ISD::SETULE:
593 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
594 case ISD::SETUNE:
595 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
596 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
597 case ISD::SETUEQ:
598 case ISD::SETOGE:
599 case ISD::SETOLE:
600 case ISD::SETONE:
601 llvm_unreachable("Invalid branch code: should be expanded by legalize");
602 // These are invalid for floating point. Assume integer.
603 case ISD::SETULT: return 0;
604 case ISD::SETUGT: return 1;
605 }
606 return 0;
607 }
608
SelectSETCC(SDNode * N)609 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
610 DebugLoc dl = N->getDebugLoc();
611 unsigned Imm;
612 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
613 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
614 bool isPPC64 = (PtrVT == MVT::i64);
615
616 if (isInt32Immediate(N->getOperand(1), Imm)) {
617 // We can codegen setcc op, imm very efficiently compared to a brcond.
618 // Check for those cases here.
619 // setcc op, 0
620 if (Imm == 0) {
621 SDValue Op = N->getOperand(0);
622 switch (CC) {
623 default: break;
624 case ISD::SETEQ: {
625 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
626 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
627 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
628 }
629 case ISD::SETNE: {
630 if (isPPC64) break;
631 SDValue AD =
632 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
633 Op, getI32Imm(~0U)), 0);
634 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
635 AD.getValue(1));
636 }
637 case ISD::SETLT: {
638 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
639 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
640 }
641 case ISD::SETGT: {
642 SDValue T =
643 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
644 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
645 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
646 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
647 }
648 }
649 } else if (Imm == ~0U) { // setcc op, -1
650 SDValue Op = N->getOperand(0);
651 switch (CC) {
652 default: break;
653 case ISD::SETEQ:
654 if (isPPC64) break;
655 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
656 Op, getI32Imm(1)), 0);
657 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
658 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
659 MVT::i32,
660 getI32Imm(0)), 0),
661 Op.getValue(1));
662 case ISD::SETNE: {
663 if (isPPC64) break;
664 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
665 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
666 Op, getI32Imm(~0U));
667 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
668 Op, SDValue(AD, 1));
669 }
670 case ISD::SETLT: {
671 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
672 getI32Imm(1)), 0);
673 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
674 Op), 0);
675 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
676 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
677 }
678 case ISD::SETGT: {
679 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
680 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
681 0);
682 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
683 getI32Imm(1));
684 }
685 }
686 }
687 }
688
689 bool Inv;
690 int OtherCondIdx;
691 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
692 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
693 SDValue IntCR;
694
695 // Force the ccreg into CR7.
696 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
697
698 SDValue InFlag(0, 0); // Null incoming flag value.
699 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
700 InFlag).getValue(1);
701
702 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
703 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
704 CCReg), 0);
705 else
706 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
707 CR7Reg, CCReg), 0);
708
709 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
710 getI32Imm(31), getI32Imm(31) };
711 if (OtherCondIdx == -1 && !Inv)
712 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
713
714 // Get the specified bit.
715 SDValue Tmp =
716 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
717 if (Inv) {
718 assert(OtherCondIdx == -1 && "Can't have split plus negation");
719 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
720 }
721
722 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
723 // We already got the bit for the first part of the comparison (e.g. SETULE).
724
725 // Get the other bit of the comparison.
726 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
727 SDValue OtherCond =
728 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
729
730 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
731 }
732
733
734 // Select - Convert the specified operand from a target-independent to a
735 // target-specific node if it hasn't already been changed.
Select(SDNode * N)736 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
737 DebugLoc dl = N->getDebugLoc();
738 if (N->isMachineOpcode())
739 return NULL; // Already selected.
740
741 switch (N->getOpcode()) {
742 default: break;
743
744 case ISD::Constant: {
745 if (N->getValueType(0) == MVT::i64) {
746 // Get 64 bit value.
747 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
748 // Assume no remaining bits.
749 unsigned Remainder = 0;
750 // Assume no shift required.
751 unsigned Shift = 0;
752
753 // If it can't be represented as a 32 bit value.
754 if (!isInt<32>(Imm)) {
755 Shift = CountTrailingZeros_64(Imm);
756 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
757
758 // If the shifted value fits 32 bits.
759 if (isInt<32>(ImmSh)) {
760 // Go with the shifted value.
761 Imm = ImmSh;
762 } else {
763 // Still stuck with a 64 bit value.
764 Remainder = Imm;
765 Shift = 32;
766 Imm >>= 32;
767 }
768 }
769
770 // Intermediate operand.
771 SDNode *Result;
772
773 // Handle first 32 bits.
774 unsigned Lo = Imm & 0xFFFF;
775 unsigned Hi = (Imm >> 16) & 0xFFFF;
776
777 // Simple value.
778 if (isInt<16>(Imm)) {
779 // Just the Lo bits.
780 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
781 } else if (Lo) {
782 // Handle the Hi bits.
783 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
784 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
785 // And Lo bits.
786 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
787 SDValue(Result, 0), getI32Imm(Lo));
788 } else {
789 // Just the Hi bits.
790 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
791 }
792
793 // If no shift, we're done.
794 if (!Shift) return Result;
795
796 // Shift for next step if the upper 32-bits were not zero.
797 if (Imm) {
798 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
799 SDValue(Result, 0),
800 getI32Imm(Shift),
801 getI32Imm(63 - Shift));
802 }
803
804 // Add in the last bits as required.
805 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
806 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
807 SDValue(Result, 0), getI32Imm(Hi));
808 }
809 if ((Lo = Remainder & 0xFFFF)) {
810 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
811 SDValue(Result, 0), getI32Imm(Lo));
812 }
813
814 return Result;
815 }
816 break;
817 }
818
819 case ISD::SETCC:
820 return SelectSETCC(N);
821 case PPCISD::GlobalBaseReg:
822 return getGlobalBaseReg();
823
824 case ISD::FrameIndex: {
825 int FI = cast<FrameIndexSDNode>(N)->getIndex();
826 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
827 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
828 if (N->hasOneUse())
829 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
830 getSmallIPtrImm(0));
831 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
832 getSmallIPtrImm(0));
833 }
834
835 case PPCISD::MFCR: {
836 SDValue InFlag = N->getOperand(1);
837 // Use MFOCRF if supported.
838 if (PPCSubTarget.isGigaProcessor())
839 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
840 N->getOperand(0), InFlag);
841 else
842 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
843 N->getOperand(0), InFlag);
844 }
845
846 case ISD::SDIV: {
847 // FIXME: since this depends on the setting of the carry flag from the srawi
848 // we should really be making notes about that for the scheduler.
849 // FIXME: It sure would be nice if we could cheaply recognize the
850 // srl/add/sra pattern the dag combiner will generate for this as
851 // sra/addze rather than having to handle sdiv ourselves. oh well.
852 unsigned Imm;
853 if (isInt32Immediate(N->getOperand(1), Imm)) {
854 SDValue N0 = N->getOperand(0);
855 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
856 SDNode *Op =
857 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
858 N0, getI32Imm(Log2_32(Imm)));
859 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
860 SDValue(Op, 0), SDValue(Op, 1));
861 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
862 SDNode *Op =
863 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
864 N0, getI32Imm(Log2_32(-Imm)));
865 SDValue PT =
866 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
867 SDValue(Op, 0), SDValue(Op, 1)),
868 0);
869 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
870 }
871 }
872
873 // Other cases are autogenerated.
874 break;
875 }
876
877 case ISD::LOAD: {
878 // Handle preincrement loads.
879 LoadSDNode *LD = cast<LoadSDNode>(N);
880 EVT LoadedVT = LD->getMemoryVT();
881
882 // Normal loads are handled by code generated from the .td file.
883 if (LD->getAddressingMode() != ISD::PRE_INC)
884 break;
885
886 SDValue Offset = LD->getOffset();
887 if (isa<ConstantSDNode>(Offset) ||
888 Offset.getOpcode() == ISD::TargetGlobalAddress) {
889
890 unsigned Opcode;
891 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
892 if (LD->getValueType(0) != MVT::i64) {
893 // Handle PPC32 integer and normal FP loads.
894 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
895 switch (LoadedVT.getSimpleVT().SimpleTy) {
896 default: llvm_unreachable("Invalid PPC load type!");
897 case MVT::f64: Opcode = PPC::LFDU; break;
898 case MVT::f32: Opcode = PPC::LFSU; break;
899 case MVT::i32: Opcode = PPC::LWZU; break;
900 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
901 case MVT::i1:
902 case MVT::i8: Opcode = PPC::LBZU; break;
903 }
904 } else {
905 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
906 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
907 switch (LoadedVT.getSimpleVT().SimpleTy) {
908 default: llvm_unreachable("Invalid PPC load type!");
909 case MVT::i64: Opcode = PPC::LDU; break;
910 case MVT::i32: Opcode = PPC::LWZU8; break;
911 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
912 case MVT::i1:
913 case MVT::i8: Opcode = PPC::LBZU8; break;
914 }
915 }
916
917 SDValue Chain = LD->getChain();
918 SDValue Base = LD->getBasePtr();
919 SDValue Ops[] = { Offset, Base, Chain };
920 // FIXME: PPC64
921 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
922 PPCLowering.getPointerTy(),
923 MVT::Other, Ops, 3);
924 } else {
925 llvm_unreachable("R+R preindex loads not supported yet!");
926 }
927 }
928
929 case ISD::AND: {
930 unsigned Imm, Imm2, SH, MB, ME;
931
932 // If this is an and of a value rotated between 0 and 31 bits and then and'd
933 // with a mask, emit rlwinm
934 if (isInt32Immediate(N->getOperand(1), Imm) &&
935 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
936 SDValue Val = N->getOperand(0).getOperand(0);
937 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
938 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
939 }
940 // If this is just a masked value where the input is not handled above, and
941 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
942 if (isInt32Immediate(N->getOperand(1), Imm) &&
943 isRunOfOnes(Imm, MB, ME) &&
944 N->getOperand(0).getOpcode() != ISD::ROTL) {
945 SDValue Val = N->getOperand(0);
946 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
947 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
948 }
949 // AND X, 0 -> 0, not "rlwinm 32".
950 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
951 ReplaceUses(SDValue(N, 0), N->getOperand(1));
952 return NULL;
953 }
954 // ISD::OR doesn't get all the bitfield insertion fun.
955 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
956 if (isInt32Immediate(N->getOperand(1), Imm) &&
957 N->getOperand(0).getOpcode() == ISD::OR &&
958 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
959 unsigned MB, ME;
960 Imm = ~(Imm^Imm2);
961 if (isRunOfOnes(Imm, MB, ME)) {
962 SDValue Ops[] = { N->getOperand(0).getOperand(0),
963 N->getOperand(0).getOperand(1),
964 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
965 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
966 }
967 }
968
969 // Other cases are autogenerated.
970 break;
971 }
972 case ISD::OR:
973 if (N->getValueType(0) == MVT::i32)
974 if (SDNode *I = SelectBitfieldInsert(N))
975 return I;
976
977 // Other cases are autogenerated.
978 break;
979 case ISD::SHL: {
980 unsigned Imm, SH, MB, ME;
981 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
982 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
983 SDValue Ops[] = { N->getOperand(0).getOperand(0),
984 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
985 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
986 }
987
988 // Other cases are autogenerated.
989 break;
990 }
991 case ISD::SRL: {
992 unsigned Imm, SH, MB, ME;
993 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
994 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
995 SDValue Ops[] = { N->getOperand(0).getOperand(0),
996 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
997 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
998 }
999
1000 // Other cases are autogenerated.
1001 break;
1002 }
1003 case ISD::SELECT_CC: {
1004 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1005 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1006 bool isPPC64 = (PtrVT == MVT::i64);
1007
1008 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1009 if (!isPPC64)
1010 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1011 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1012 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1013 if (N1C->isNullValue() && N3C->isNullValue() &&
1014 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1015 // FIXME: Implement this optzn for PPC64.
1016 N->getValueType(0) == MVT::i32) {
1017 SDNode *Tmp =
1018 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1019 N->getOperand(0), getI32Imm(~0U));
1020 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1021 SDValue(Tmp, 0), N->getOperand(0),
1022 SDValue(Tmp, 1));
1023 }
1024
1025 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1026 unsigned BROpc = getPredicateForSetCC(CC);
1027
1028 unsigned SelectCCOp;
1029 if (N->getValueType(0) == MVT::i32)
1030 SelectCCOp = PPC::SELECT_CC_I4;
1031 else if (N->getValueType(0) == MVT::i64)
1032 SelectCCOp = PPC::SELECT_CC_I8;
1033 else if (N->getValueType(0) == MVT::f32)
1034 SelectCCOp = PPC::SELECT_CC_F4;
1035 else if (N->getValueType(0) == MVT::f64)
1036 SelectCCOp = PPC::SELECT_CC_F8;
1037 else
1038 SelectCCOp = PPC::SELECT_CC_VRRC;
1039
1040 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1041 getI32Imm(BROpc) };
1042 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1043 }
1044 case PPCISD::COND_BRANCH: {
1045 // Op #0 is the Chain.
1046 // Op #1 is the PPC::PRED_* number.
1047 // Op #2 is the CR#
1048 // Op #3 is the Dest MBB
1049 // Op #4 is the Flag.
1050 // Prevent PPC::PRED_* from being selected into LI.
1051 SDValue Pred =
1052 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1053 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1054 N->getOperand(0), N->getOperand(4) };
1055 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1056 }
1057 case ISD::BR_CC: {
1058 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1059 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1060 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1061 N->getOperand(4), N->getOperand(0) };
1062 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1063 }
1064 case ISD::BRIND: {
1065 // FIXME: Should custom lower this.
1066 SDValue Chain = N->getOperand(0);
1067 SDValue Target = N->getOperand(1);
1068 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1069 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1070 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
1071 Chain), 0);
1072 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1073 }
1074 }
1075
1076 return SelectCode(N);
1077 }
1078
1079
1080
1081 /// createPPCISelDag - This pass converts a legalized DAG into a
1082 /// PowerPC-specific DAG, ready for instruction scheduling.
1083 ///
createPPCISelDag(PPCTargetMachine & TM)1084 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1085 return new PPCDAGToDAGISel(TM);
1086 }
1087
1088