Home
last modified time | relevance | path

Searched refs:RS (Results 1 – 25 of 535) sorted by relevance

12345678910>>...22

/external/valgrind/none/tests/mips64/
Dmacro_int.h1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \ argument
5 "move $"#RS", %1" "\n\t" \
12 : #RD, #RS, #RT \
19 #define TEST2(instruction, RSval, imm, RT, RS) \ argument
23 "move $"#RS", %1" "\n\t" \
29 : #RT, #RS \
35 #define TEST3(instruction, RSval, RD, RS) \ argument
39 "move $"#RS", %1" "\n\t" \
45 : #RD, #RS \
51 #define TEST4(instruction, RSval, RTval, RS, RT) \ argument
[all …]
Dbranches.c130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
135 "move $"#RS", %1" "\n\t" \
138 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
147 : #RD, #RS, #RT \
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
158 "move $"#RS", %1" "\n\t" \
160 instruction" $"#RS", end"instruction#RDval "\n\t" \
169 : #RD, #RS \
175 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
181 "move $"#RS", %1" "\n\t" \
[all …]
Dbranch_and_jump_instructions.c107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
112 "move $"#RS", %1" "\n\t" \
115 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
124 : #RD, #RS, #RT \
130 #define TEST4(instruction, RDval, RSval, RD, RS) \ argument
135 "move $"#RS", %1" "\n\t" \
137 instruction" $"#RS", end"instruction#RDval "\n\t" \
146 : #RD, #RS \
152 #define TEST5(instruction, RDval, RSval, RD, RS) \ argument
158 "move $"#RS", %1" "\n\t" \
[all …]
Dcvm_ins.c70 #define TESTINST1(instruction, RSVal, RT, RS, p, lenm1) \ argument
75 "move $" #RS ", %1" "\n\t" \
80 : #RS, #RT, "cc", "memory" \
85 #define TESTINST2(instruction, RSVal, RTval, RD, RS, RT) \ argument
90 "move $" #RS ", %1" "\n\t" \
96 : #RD, #RS, #RT, "cc", "memory" \
101 #define TESTINST3(instruction, RSVal, RT, RS, imm) \ argument
106 "move $" #RS ", %1" "\n\t" \
111 : #RS, #RT, "cc", "memory" \
Dload_store_multiple.c23 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
27 "move $"#RS", %1" "\n\t" \
30 "lw %0, "#offset"($"#RS")" "\n\t" \
33 : #RT, #RS \
39 "move $"#RS", %1" "\n\t" \
42 "lw %0, "#offset"($"#RS")" "\n\t" \
45 : #RT, #RS \
53 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
57 "move $"#RS", %1" "\n\t" \
58 "daddiu $"#RS", $"#RS", "#offset "\n\t" \
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCJITInfo.cpp27 #define BUILD_ADDIS(RD,RS,IMM16) \ argument
28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
29 #define BUILD_ORI(RD,RS,UIMM16) \ argument
30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
31 #define BUILD_ORIS(RD,RS,UIMM16) \ argument
32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
33 #define BUILD_RLDICR(RD,RS,SH,ME) \ argument
34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
36 #define BUILD_MTSPR(RS,SPR) \ argument
37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
[all …]
DPPCRegisterInfo.h54 int SPAdj, RegScavenger *RS) const;
56 int SPAdj, RegScavenger *RS) const;
58 int SPAdj, RegScavenger *RS = NULL) const;
/external/llvm/lib/CodeGen/
DPrologEpilogInserter.cpp51 static void doSpillCalleeSavedRegs(MachineFunction &MF, RegScavenger *RS,
57 static void doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS);
93 std::function<void(MachineFunction &MF, RegScavenger *RS,
98 std::function<void(MachineFunction &MF, RegScavenger *RS)>
103 RegScavenger *RS; member in __anon77e2d1720111::PEI
177 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr; in runOnMachineFunction()
190 SpillCalleeSavedRegisters(Fn, RS, MinCSFrameIndex, MaxCSFrameIndex, in runOnMachineFunction()
195 TFI->processFunctionBeforeFrameFinalized(Fn, RS); in runOnMachineFunction()
217 ScavengeFrameVirtualRegs(Fn, RS); in runOnMachineFunction()
231 delete RS; in runOnMachineFunction()
[all …]
DShrinkWrap.cpp135 bool useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS) const;
137 const SetOfRegs &getCurrentCSRs(RegScavenger *RS) const { in getCurrentCSRs()
143 TFI->determineCalleeSaves(*MachineFunc, SavedRegs, RS); in getCurrentCSRs()
157 void updateSaveRestorePoints(MachineBasicBlock &MBB, RegScavenger *RS);
224 RegScavenger *RS) const { in INITIALIZE_PASS_DEPENDENCY()
241 for (unsigned Reg : getCurrentCSRs(RS)) { in INITIALIZE_PASS_DEPENDENCY()
273 RegScavenger *RS) { in updateSaveRestorePoints() argument
294 if (!useOrDefCSROrFI(Terminator, RS)) in updateSaveRestorePoints()
443 std::unique_ptr<RegScavenger> RS( in runOnMachineFunction() local
456 if (!useOrDefCSROrFI(MI, RS.get())) in runOnMachineFunction()
[all …]
/external/valgrind/none/tests/mips32/
Dbranches.c129 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \ argument
135 "move $" #RS ", %1\n\t" \
138 instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
147 : #RD, #RS, #RT, "memory" \
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \ argument
159 "move $" #RS ", %1\n\t" \
161 instruction" $" #RS ", end"instruction#RDval"\n\t" \
170 : #RD, #RS, "memory" \
176 #define TESTINST6(instruction, RDval, RSval, RD, RS) \ argument
183 "move $" #RS ", %1\n\t" \
[all …]
DLoadStore1.c24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
28 "move $" #RS", %1 \n\t" \
31 "lw %0, "#offset"($"#RS") \n\t" \
34 : #RS, #RT, "memory" \
40 "move $" #RS", %1 \n\t" \
43 "lw %0, "#offset"($"#RS") \n\t" \
46 : #RS, #RT, "memory" \
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
58 "move $" #RS", %1\n\t" \
59 "addiu $"#RS", $"#RS", "#offset" \n\t" \
[all …]
DLoadStore.c24 #define TESTINST1(instruction, RTval, offset, RT, RS) \ argument
28 "move $" #RS", %1 \n\t" \
31 "lw %0, "#offset"($"#RS") \n\t" \
34 : #RS, #RT, "memory" \
40 "move $" #RS", %1 \n\t" \
43 "lw %0, "#offset"($"#RS") \n\t" \
46 : #RS, #RT, "memory" \
54 #define TESTINSTsw(RTval, offset, RT, RS) \ argument
58 "move $" #RS", %1\n\t" \
59 "addiu $"#RS", $"#RS", "#offset" \n\t" \
[all …]
Dmips32_dspr2.c92 #define TESTDSPINST_RD_RS_RT_DSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
100 "move $" #RS ", %2 \n\t" \
107 : #RD, #RS, #RT \
134 #define TESTDSPINST_RS_RT_DSPC(instruction, RSval, RTval, RS, RT) \ argument
140 "move $" #RS ", %1 \n\t" \
146 : #RS, #RT \
152 #define TESTDSPINST_RD_RS_RT_NODSPC(instruction, RSval, RTval, RD, RS, RT) \ argument
158 "move $" #RS ", %1 \n\t" \
164 : #RD, #RS, #RT \
171 RS, RT) \
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp96 int Offset, RegScavenger *RS ) { in InsertFPConstInst() argument
97 assert(RS && "requiresRegisterScavenging failed"); in InsertFPConstInst()
101 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertFPConstInst()
102 RS->setRegUsed(ScratchOffset); in InsertFPConstInst()
164 unsigned Reg, int Offset, RegScavenger *RS ) { in InsertSPConstInst() argument
165 assert(RS && "requiresRegisterScavenging failed"); in InsertSPConstInst()
173 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
174 RS->setRegUsed(ScratchBase); in InsertSPConstInst()
178 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0); in InsertSPConstInst()
179 RS->setRegUsed(ScratchOffset); in InsertSPConstInst()
[all …]
/external/llvm/include/llvm/CodeGen/
DRegAllocPBQP.h195 : RS(Unprocessed), NumOpts(0), DeniedOpts(0), OptUnsafeEdges(nullptr), in NodeMetadata()
205 : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts), in NodeMetadata()
221 : RS(Other.RS), NumOpts(Other.NumOpts), DeniedOpts(Other.DeniedOpts), in NodeMetadata()
232 RS = Other.RS;
249 RS = Other.RS;
274 ReductionState getReductionState() const { return RS; } in getReductionState()
275 void setReductionState(ReductionState RS) { in setReductionState() argument
276 assert(RS >= this->RS && "A node's reduction state can not be downgraded"); in setReductionState()
277 this->RS = RS; in setReductionState()
282 if (RS == ConservativelyAllocatable) in setReductionState()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DPrologEpilogInserter.cpp74 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; in runOnMachineFunction()
84 TFI->processFunctionBeforeCalleeSavedScan(Fn, RS); in runOnMachineFunction()
128 delete RS; in runOnMachineFunction()
566 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) && in calculateFrameObjectOffsets()
568 int SFI = RS->getScavengingFrameIndex(); in calculateFrameObjectOffsets()
613 if (RS && (int)i == RS->getScavengingFrameIndex()) in calculateFrameObjectOffsets()
635 if (RS && (int)i == RS->getScavengingFrameIndex()) in calculateFrameObjectOffsets()
649 if (RS && (!TFI.hasFP(Fn) || RegInfo->needsStackRealignment(Fn) || in calculateFrameObjectOffsets()
651 int SFI = RS->getScavengingFrameIndex(); in calculateFrameObjectOffsets()
735 if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB); in replaceFrameIndices()
[all …]
/external/clang/lib/StaticAnalyzer/Checkers/
DMallocChecker.cpp94 static RefState getAllocatedOfSizeZero(const RefState *RS) { in getAllocatedOfSizeZero() argument
95 return RefState(AllocatedOfSizeZero, RS->getStmt(), in getAllocatedOfSizeZero()
96 RS->getAllocationFamily()); in getAllocatedOfSizeZero()
104 static RefState getEscaped(const RefState *RS) { in getEscaped() argument
105 return RefState(Escaped, RS->getStmt(), RS->getAllocationFamily()); in getEscaped()
373 const Expr *DeallocExpr, const RefState *RS,
905 const RefState *RS = State->get<RegionState>(Sym); in ProcessZeroAllocation() local
906 if (RS) { in ProcessZeroAllocation()
907 if (RS->isAllocated()) in ProcessZeroAllocation()
909 RefState::getAllocatedOfSizeZero(RS)); in ProcessZeroAllocation()
[all …]
DReturnPointerRangeChecker.cpp31 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
35 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
39 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
/external/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp36 RegisterSet(const RegisterSet &RS) : BitVector(RS) {} in RegisterSet()
118 : RS(S), TRI(RI) {} in PrintRegSet()
122 const RegisterSet &RS; member
130 for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) in operator <<()
184 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
881 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) { in isTransparentCopy() argument
883 !TargetRegisterInfo::isVirtualRegister(RS.Reg)) in isTransparentCopy()
890 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1013 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
1226 BitTracker::RegisterRef RS) { in usedBitsEqual() argument
[all …]
/external/llvm/test/CodeGen/PowerPC/
DFrames-alloca.ll6 …N: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=CHECK-PPC32-RS
7 …32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=CHECK-PPC32-RS-NOFP
15 ; CHECK-PPC32-RS: stwu r1, -48(r1)
16 ; CHECK-PPC32-RS-NOFP: stwu r1, -48(r1)
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
DFrames-alloca.ll6 …c32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
7 …pple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
15 ; CHECK-PPC32-RS: stwu r1, -80(r1)
16 ; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1)
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.cpp179 RegScavenger *RS, in findScratchRegister() argument
182 assert(RS && "Register scavenging must be on"); in findScratchRegister()
183 unsigned Reg = RS->FindUnusedReg(RC); in findScratchRegister()
185 Reg = RS->scavengeRegister(RC, II, SPAdj); in findScratchRegister()
191 int SPAdj, RegScavenger *RS) const { in eliminateFrameIndex()
267 unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj); in eliminateFrameIndex()
282 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj); in eliminateFrameIndex()
304 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj); in eliminateFrameIndex()
/external/llvm/include/llvm/DebugInfo/DWARF/
DDWARFUnit.h48 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS,
82 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS, in parseImpl() argument
91 auto U = llvm::make_unique<UnitType>(Context, Section, DA, RS, SS, SOS, in parseImpl()
148 const DWARFDebugAbbrev *DA, StringRef RS, StringRef SS,
164 void setRangesSection(StringRef RS, uint32_t Base) { in setRangesSection() argument
165 RangeSection = RS; in setRangesSection()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.h93 RegScavenger *RS = nullptr) const override;
95 RegScavenger *RS = nullptr) const override;
96 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPURegisterInfo.cpp255 RegScavenger *RS) const in eliminateFrameIndex()
299 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj); in eliminateFrameIndex()
346 RegScavenger *RS, in findScratchRegister() argument
350 assert(RS && "Register scavenging must be on"); in findScratchRegister()
351 unsigned Reg = RS->FindUnusedReg(RC); in findScratchRegister()
353 Reg = RS->scavengeRegister(RC, II, SPAdj); in findScratchRegister()

12345678910>>...22