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Searched refs:RSP (Results 1 – 25 of 67) sorted by relevance

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/external/libunwind/src/x86_64/
DGstash_frame.c42 rs->reg[RSP].where, rs->reg[RSP].val, DWARF_GET_LOC(d->loc[RSP])); in tdep_stash_frame()
52 || rs->reg[DWARF_CFA_REG_COLUMN].val == RSP) in tdep_stash_frame()
60 && (rs->reg[RSP].where == DWARF_WHERE_UNDEF in tdep_stash_frame()
61 || rs->reg[RSP].where == DWARF_WHERE_SAME in tdep_stash_frame()
62 || (rs->reg[RSP].where == DWARF_WHERE_CFAREL in tdep_stash_frame()
63 && labs(rs->reg[RSP].val) < (1 << 14) in tdep_stash_frame()
64 && rs->reg[RSP].val+1 != 0))) in tdep_stash_frame()
68 f->cfa_reg_rsp = (rs->reg[DWARF_CFA_REG_COLUMN].val == RSP); in tdep_stash_frame()
72 if (rs->reg[RSP].where == DWARF_WHERE_CFAREL) in tdep_stash_frame()
73 f->rsp_cfa_offset = rs->reg[RSP].val; in tdep_stash_frame()
[all …]
Dinit.h56 c->dwarf.loc[RSP] = REG_INIT_LOC(c, rsp, RSP); in common_init()
DGget_save_loc.c41 case UNW_X86_64_RSP: loc = c->dwarf.loc[RSP]; break; in unw_get_save_loc()
Dunwind_i.h46 #define RSP 7 macro
/external/llvm/test/CodeGen/X86/
Dstatepoint-stackmap-format.ll127 ; Indirect Spill Slot [RSP+0]
147 ; Indirect Spill Slot [RSP+16]
152 ; Indirect Spill Slot [RSP+8]
157 ; Indirect Spill Slot [RSP+16]
162 ; Indirect Spill Slot [RSP+16]
194 ; Indirect Spill Slot [RSP+0]
214 ; Indirect Spill Slot [RSP+16]
219 ; Indirect Spill Slot [RSP+8]
224 ; Indirect Spill Slot [RSP+16]
229 ; Indirect Spill Slot [RSP+16]
Dstatepoint-allocas.ll91 ; Direct Spill Slot [RSP+0]
120 ; Direct Spill Slot [RSP+0]
Dstackmap-liveness.ll122 ; LiveOut Entry 1: %RSP (8 bytes)
159 ; LiveOut Entry 1: %RSP (8 bytes)
/external/llvm/test/MC/X86/
Dintel-syntax-2.s6 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP - 4], 255
Dintel-syntax.s11 mov DWORD PTR [RSP - 4], 257
13 mov DWORD PTR [RSP + 4], 258
15 mov QWORD PTR [RSP - 16], 123
17 mov BYTE PTR [RSP - 17], 97
19 mov EAX, DWORD PTR [RSP - 4]
21 mov RAX, QWORD PTR [RSP]
23 mov DWORD PTR [RSP - 4], -4
27 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
Dintel-syntax-encoding.s25 mov QWORD PTR [RSP - 16], RAX
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, in initLLVMToSEHAndCVRegMapping()
187 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
291 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
319 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
356 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
392 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
428 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegisterOrZero()
429 return X86::RSP; in getX86SubSuperRegisterOrZero()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td211 // All calls clobber the non-callee saved registers. RSP is marked as
220 Uses = [RSP] in {
243 // All calls clobber the non-callee saved registers. RSP is marked as
251 Uses = [RSP] in {
268 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
269 let Defs = [RAX, R10, R11, RSP, EFLAGS],
270 Uses = [RSP] in {
284 Uses = [RSP],
DX86RegisterInfo.cpp69 StackPtr = X86::RSP; in X86RegisterInfo()
394 Reserved.set(X86::RSP); in getReservedRegs()
695 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
732 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
768 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
804 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: in getX86SubSuperRegister()
805 return X86::RSP; in getX86SubSuperRegister()
DX86CompilationCallback_Win64.asm20 ; Save RSP.
DX86RegisterInfo.td131 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
314 RBX, R14, R15, R12, R13, RBP, RSP, RIP)> {
387 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)> {
405 // GR64_NOSP - GR64 registers except RSP (and RIP).
406 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)> {
420 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
/external/llvm/test/DebugInfo/COFF/
Dlocal-variables.ll30 ; ASM: #DEBUG_VALUE: f:param <- [%RSP+52]
38 ; ASM: #DEBUG_VALUE: f:param <- [%RSP+52]
39 ; ASM: #DEBUG_VALUE: a <- [%RSP+40]
52 ; ASM: #DEBUG_VALUE: f:param <- [%RSP+52]
53 ; ASM: #DEBUG_VALUE: b <- [%RSP+36]
/external/strace/linux/x86_64/
Duserent.h20 XLAT(8*RSP),
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmInstrumentation.cpp115 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; } in IsStackReg()
798 if (FrameReg == X86::RSP) { in InstrumentMemOperandPrologue()
836 if (FrameReg == X86::RSP) in InstrumentMemOperandEpilogue()
858 X86Operand::CreateMem(getPointerWidth(), 0, Disp, X86::RSP, 0, 1, in EmitAdjustRSP()
860 EmitLEA(*Op, 64, X86::RSP, Out); in EmitAdjustRSP()
870 .addReg(X86::RSP) in EmitCallAsanReport()
871 .addReg(X86::RSP) in EmitCallAsanReport()
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h58 #define RSP 152 macro
/external/capstone/suite/MC/X86/
Dintel-syntax-encoding.s.cs11 0x48,0x89,0x44,0x24,0xf0 = mov QWORD PTR [RSP - 16], RAX
/external/valgrind/coregrind/m_sigframe/
Dsigframe-amd64-darwin.c108 SC2(__rsp,RSP); in synthesize_ucontext()
136 SC2(RSP,__rsp); in restore_from_ucontext()
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp585 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
588 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
601 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP); in emitStackProbeInline()
665 X86::RSP, false, RCXShadowSlot); in emitStackProbeInline()
668 X86::RSP, false, RDXShadowSlot); in emitStackProbeInline()
673 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP) in emitStackProbeInline()
674 .addReg(X86::RSP) in emitStackProbeInline()
745 unsigned SP = Is64Bit ? X86::RSP : X86::ESP; in emitStackProbeCall()
756 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP) in emitStackProbeCall()
757 .addReg(X86::RSP) in emitStackProbeCall()
[all …]
DX86RegisterInfo.td136 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
350 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
396 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
406 // GR64_NOSP - GR64 registers except RSP (and RIP).
407 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
414 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp149 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: in getX86RegNum()
322 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth); in createX86MCAsmInfo()
326 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth); in createX86MCAsmInfo()
/external/lzma/Asm/x86/
D7zAsm.asm70 r4 equ RSP

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