Home
last modified time | relevance | path

Searched refs:RVLocs (Results 1 – 25 of 31) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp231 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
235 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerReturn()
243 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
244 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
250 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
251 CCValAssign &VA = RVLocs[i]; in LowerReturn()
382 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
384 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerCall()
389 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCall()
390 CCValAssign &RV = RVLocs[i]; in LowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp518 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
520 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
525 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
526 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
561 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
565 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
573 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
574 if (RVLocs[i].isRegLoc()) in LowerReturn()
575 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
581 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp841 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
843 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
848 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
849 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
850 RVLocs[i].getValVT(), InFlag).getValue(1); in LowerCallResult()
1014 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1018 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
1026 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
1027 if (RVLocs[i].isRegLoc()) in LowerReturn()
1028 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp390 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
400 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
408 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
409 if (RVLocs[i].isRegLoc()) in LowerReturn()
410 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
416 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
417 CCValAssign &VA = RVLocs[i]; in LowerReturn()
575 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
577 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
582 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp352 SmallVectorImpl<CCValAssign> &RVLocs, in AnalyzeReturnValues() argument
358 std::reverse(RVLocs.begin(), RVLocs.end()); in AnalyzeReturnValues()
512 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
519 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
523 AnalyzeReturnValues(CCInfo, RVLocs, Outs); in LowerReturn()
529 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
530 CCValAssign &VA = RVLocs[i]; in LowerReturn()
697 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
698 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
701 AnalyzeReturnValues(CCInfo, RVLocs, Ins); in LowerCallResult()
[all …]
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp353 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
357 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
371 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
372 CCValAssign &VA = RVLocs[i]; in LowerReturn()
399 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
400 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerCallResult()
412 for (auto &Val : RVLocs) { in LowerCallResult()
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp1028 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1030 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
1035 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
1036 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
1037 RVLocs[i].getValVT(), InFlag).getValue(1); in LowerCallResult()
1198 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1199 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); in CanLowerReturn()
1212 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1216 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
1224 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcISelLowering.cpp90 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
94 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerReturn()
102 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
103 if (RVLocs[i].isRegLoc()) in LowerReturn()
104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
110 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
111 CCValAssign &VA = RVLocs[i]; in LowerReturn()
592 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
594 DAG.getTarget(), RVLocs, *DAG.getContext()); in LowerCall()
599 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86FastISel.cpp1867 SmallVector<CCValAssign, 16> RVLocs; in DoSelectCall() local
1868 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs, in DoSelectCall()
1872 for (unsigned i = 0; i != RVLocs.size(); ++i) { in DoSelectCall()
1873 EVT CopyVT = RVLocs[i].getValVT(); in DoSelectCall()
1879 if ((RVLocs[i].getLocReg() == X86::ST0 || in DoSelectCall()
1880 RVLocs[i].getLocReg() == X86::ST1)) { in DoSelectCall()
1881 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) { in DoSelectCall()
1889 CopyReg).addReg(RVLocs[i].getLocReg()); in DoSelectCall()
1890 UsedRegs.push_back(RVLocs[i].getLocReg()); in DoSelectCall()
1893 if (CopyVT != RVLocs[i].getValVT()) { in DoSelectCall()
[all …]
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp2027 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2028 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); in FinishCall()
2032 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
2035 MVT DestVT = RVLocs[0].getValVT(); in FinishCall()
2040 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2041 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2043 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2044 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
2049 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); in FinishCall()
2050 MVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp1679 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
1680 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); in FinishCall()
1684 if (RVLocs.size() == 2 && RetVT == MVT::f64) { in FinishCall()
1687 EVT DestVT = RVLocs[0].getValVT(); in FinishCall()
1692 .addReg(RVLocs[0].getLocReg()) in FinishCall()
1693 .addReg(RVLocs[1].getLocReg())); in FinishCall()
1695 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
1696 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
1701 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); in FinishCall()
1702 EVT CopyVT = RVLocs[0].getValVT(); in FinishCall()
[all …]
DARMISelLowering.cpp1109 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
1111 getTargetMachine(), RVLocs, *DAG.getContext(), Call); in LowerCallResult()
1117 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
1118 CCValAssign VA = RVLocs[i]; in LowerCallResult()
1127 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1139 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1143 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1772 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1776 getTargetMachine(), RVLocs, *DAG.getContext(), Call); in LowerReturn()
1785 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1071 const SmallVectorImpl<CCValAssign> &RVLocs, in LowerCallResult() argument
1076 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
1077 const CCValAssign &VA = RVLocs[i]; in LowerCallResult()
1134 SmallVector<CCValAssign, 16> RVLocs; in LowerCCCCallTo() local
1136 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCCCCallTo()
1239 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); in LowerCCCCallTo()
1438 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
1439 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); in CanLowerReturn()
1460 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1463 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp214 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_32() local
217 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
230 i != RVLocs.size(); in LowerReturn_32()
232 CCValAssign &VA = RVLocs[i]; in LowerReturn_32()
252 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
297 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn_64() local
300 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_64()
314 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn_64()
315 CCValAssign &VA = RVLocs[i]; in LowerReturn_64()
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
[all …]
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp525 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
528 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
538 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
539 CCValAssign &VA = RVLocs[i]; in LowerReturn()
767 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
768 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
774 for (unsigned I = 0; I != RVLocs.size(); ++I) { in LowerCallResult()
775 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), in LowerCallResult()
776 RVLocs[I].getValVT(), InFlag) in LowerCallResult()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp2196 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2198 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
2203 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2204 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
2205 RVLocs[i].getValVT(), InFlag).getValue(1); in LowerCallResult()
2426 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
2430 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
2438 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
2439 if (RVLocs[i].isRegLoc()) in LowerReturn()
2440 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1405 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1406 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1408 CCValAssign &VA = RVLocs[0]; in finishCall()
1409 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); in finishCall()
1494 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
1495 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context); in fastLowerCall()
1497 if (RVLocs.size() > 1) in fastLowerCall()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1225 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
1226 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
1230 if (RVLocs.size() != 1) in finishCall()
1233 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
1243 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1244 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
DMipsISelLowering.cpp2904 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2905 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
2910 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
2911 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
2914 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2915 RVLocs[i].getLocVT(), InFlag); in LowerCallResult()
3181 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3182 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); in CanLowerReturn()
3216 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
3220 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp355 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
357 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
362 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
363 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp563 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
566 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
576 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
577 CCValAssign &VA = RVLocs[i]; in LowerReturn()
616 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
618 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
624 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCallResult()
626 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
633 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
643 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp1434 SmallVector<CCValAssign, 16> RVLocs; in LowerCall() local
1436 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCall()
1441 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerCall()
1442 CCValAssign VA = RVLocs[i]; in LowerCall()
1461 SmallVector<CCValAssign, 16> RVLocs; in LowerReturn() local
1463 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerReturn()
1469 for (unsigned i = 0; i != RVLocs.size(); ++i) in LowerReturn()
1470 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in LowerReturn()
1476 for (unsigned i = 0; i != RVLocs.size(); ++i) { in LowerReturn()
1477 CCValAssign &VA = RVLocs[i]; in LowerReturn()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp2711 SmallVector<CCValAssign, 16> RVLocs; in LowerCallResult() local
2713 getTargetMachine(), RVLocs, *DAG.getContext()); in LowerCallResult()
2717 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { in LowerCallResult()
2718 CCValAssign &VA = RVLocs[i]; in LowerCallResult()
2761 SmallVector<CCValAssign, 16> RVLocs; in FinishCall() local
2763 getTargetMachine(), RVLocs, *DAG.getContext()); in FinishCall()
2765 for (unsigned i = 0; i != RVLocs.size(); ++i) in FinishCall()
2766 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); in FinishCall()
3424 SmallVector<CCValAssign, 16> RVLocs; in CanLowerReturn() local
3426 RVLocs, Context); in CanLowerReturn()
[all …]
/external/llvm/lib/Target/X86/
DX86FastISel.cpp3346 SmallVector<CCValAssign, 16> RVLocs; in fastLowerCall() local
3347 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, in fastLowerCall()
3353 for (unsigned i = 0; i != RVLocs.size(); ++i) { in fastLowerCall()
3354 CCValAssign &VA = RVLocs[i]; in fastLowerCall()
3395 CLI.NumResultRegs = RVLocs.size(); in fastLowerCall()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp3032 SmallVector<CCValAssign, 16> RVLocs; in finishCall() local
3033 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); in finishCall()
3037 if (RVLocs.size() != 1) in finishCall()
3041 MVT CopyVT = RVLocs[0].getValVT(); in finishCall()
3050 .addReg(RVLocs[0].getLocReg()); in finishCall()
3051 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()

12