| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 36 SHL = 0x17, enumerator
93 case SHL: in lanaiAluCodeToString()
113 .Case("sh", SHL) in stringToLanaiAluCode()
135 case ISD::SHL: in isdToLanaiAluCode()
136 return AluCode::SHL; in isdToLanaiAluCode()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | shift-i64-opts.ll | 126 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]]
127 ; GCN: buffer_store_dword [[SHL]]
138 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
139 ; GCN: buffer_store_short [[SHL]]
150 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]]
151 ; GCN: buffer_store_short [[SHL]]
162 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]]
163 ; GCN: buffer_store_byte [[SHL]]
174 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]]
175 ; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 2, [[SHL]]
[all …]
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| D | trunc.ll | 24 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
25 ; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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| /external/libxaac/decoder/armv8/ |
| D | ixheaacd_sbr_imdct_using_fft.s | 343 SHL V12.4S, V12.4S, #1
346 SHL V22.4S, V22.4S, #1
348 SHL V9.4S, V9.4S, #1
351 SHL V2.4S, V2.4S, #1
353 SHL V24.4S, V24.4S, #1
356 SHL V7.4S, V7.4S, #1
358 SHL V13.4S, V13.4S, #1
361 SHL V23.4S, V23.4S, #1
363 SHL V10.4S, V10.4S, #1
366 SHL V3.4S, V3.4S, #1
[all …]
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| D | ixheaacd_imdct_using_fft.s | 393 SHL v12.4S, v12.4S, #3
396 SHL v22.4S, v22.4S, #3
398 SHL v9.4S, v9.4S, #3
401 SHL v2.4S, v2.4S, #3
403 SHL v24.4S, v24.4S, #3
406 SHL v7.4S, v7.4S, #3
408 SHL v13.4S, v13.4S, #3
411 SHL v23.4S, v23.4S, #3
413 SHL v10.4S, v10.4S, #3
416 SHL v3.4S, v3.4S, #3
[all …]
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| D | ixheaacd_inv_dit_fft_8pt.s | 109 SHL v7.4s, v7.4s, #1
110 SHL v10.4s, v10.4s, #1
131 SHL v9.4s, v9.4s, #1
132 SHL v13.4s, v13.4s, #1
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | p8-scalar_vector_conversions.ll | 687 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
688 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
698 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
699 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
721 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3
722 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
732 ; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3
733 ; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]]
1039 ; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4
1040 ; CHECK-DAG: srd 3, [[MOV]], [[SHL]]
[all …]
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| D | load-v4i8-improved.ll | 20 ; CHECK-BE: sldi [[SHL:[0-9]+]], [[GPR]], 32
21 ; CHECK-BE: mtvsrd [[VSR:[0-9]+]], [[SHL]]
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
138 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
151 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
154 { ISD::SHL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
157 { ISD::SHL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
159 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
178 { ISD::SHL, MVT::v16i8, 1 }, in getArithmeticInstrCost()
181 { ISD::SHL, MVT::v8i16, 1 }, in getArithmeticInstrCost()
184 { ISD::SHL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
[all …]
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| /external/llvm/test/Transforms/InstSimplify/ |
| D | shift-knownbits.ll | 74 ; CHECK-NEXT: [[SHL:%.*]] = shl i9 %a, [[AND]]
75 ; CHECK-NEXT: ret i9 [[SHL]]
98 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[OR]]
99 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
128 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %a, [[AND]]
129 ; CHECK-NEXT: ret <2 x i32> [[SHL]]
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| D | shift-128-kb.ll | 14 ; CHECK-NEXT: [[SHL:%.*]] = shl i128 [[CONV2]], [[SH_PROM]]
15 ; CHECK-NEXT: [[SHR:%.*]] = ashr i128 [[SHL]], [[SH_PROM]]
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUNodes.td | 86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
87 def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>;
105 // SHL_BITS the same as SHL for i128, but ISD::SHL is not implemented for i128
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| /external/llvm/test/Transforms/InstCombine/ |
| D | rem.ll | 68 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
69 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
146 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
147 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
159 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
160 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
198 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i32 [[EXT]], 3
199 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 63
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| D | strchr-1.ll | 86 ; CHECK-NEXT: [[SHL:%.*]] = shl i16 1, [[TRUNC]]
87 ; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHL]], 9217
|
| /external/libopus/celt/ |
| D | fixed_generic.h | 57 #define MULT16_32_Q15(a,b) ADD32(SHL(MULT16_16((a),SHR((b),16)),1), SHR(MULT16_16SU((a),((b)&0x0000…
64 #define MULT32_32_Q31(a,b) ADD32(ADD32(SHL(MULT16_16(SHR((a),16),SHR((b),16)),1), SHR(MULT16_16SU(S…
99 #define SHL(a,shift) SHL32(a,shift) macro
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 346 if (Opcode == ISD::SHL) { in isRotateAndMask()
397 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
399 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
407 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
422 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; in SelectBitfieldInsert()
426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && in SelectBitfieldInsert()
429 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; in SelectBitfieldInsert()
979 case ISD::SHL: { in Select()
|
| /external/skia/src/sksl/ |
| D | SkSLLexer.h | 136 #undef SHL
137 SHL, enumerator
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| /external/skqp/src/sksl/ |
| D | SkSLLexer.h | 136 #undef SHL
137 SHL, enumerator
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 70 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; in PromoteIntegerResult()
528 return DAG.getNode(ISD::SHL, N->getDebugLoc(), in PromoteIntRes_SHL()
717 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
784 case ISD::SHL: in PromoteIntegerOperand()
889 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, in PromoteIntOp_BUILD_PAIR()
1148 case ISD::SHL: in ExpandIntegerResult()
1266 if (N->getOpcode() == ISD::SHL) { in ExpandShiftByConstant()
1271 Hi = DAG.getNode(ISD::SHL, DL, in ExpandShiftByConstant()
1286 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
1288 DAG.getNode(ISD::SHL, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_vec4_gs_visitor.cpp | 379 inst = emit(SHL(dst_reg(channel_mask), one, channel)); in emit_control_data_bits()
430 emit(SHL(dst_reg(shift_count), this->vertex_count, brw_imm_ud(1u))); in set_stream_control_data_bits()
438 emit(SHL(dst_reg(mask), sid, shift_count)); in set_stream_control_data_bits()
583 emit(SHL(dst_reg(mask), one, prev_count)); in gs_end_primitive()
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| D | brw_fs_surface_builder.cpp | 610 bld.SHL(tmp, major, offset(tile, bld, 1)); in emit_address_calculation()
612 bld.SHL(tmp, tmp, offset(tile, bld, 0)); in emit_address_calculation()
614 bld.SHL(offset(tmp, bld, 1), in emit_address_calculation()
694 bld.SHL(tmp, offset(src, bld, c), brw_imm_ud(shifts[c] % 32)); in emit_pack()
724 bld.SHL(offset(dst, bld, c), in emit_unpack()
878 bld.SHL(offset(dst, bld, c), in emit_convert_from_float()
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| /external/v8/src/ic/ |
| D | ic-state.cc | 170 GENERATE(Token::SHL, INT32, SMI, INT32); in GenerateAheadOfTime()
171 GENERATE(Token::SHL, INT32, SMI, SMI); in GenerateAheadOfTime()
172 GENERATE(Token::SHL, NUMBER, SMI, SMI); in GenerateAheadOfTime()
173 GENERATE(Token::SHL, SMI, SMI, INT32); in GenerateAheadOfTime()
174 GENERATE(Token::SHL, SMI, SMI, SMI); in GenerateAheadOfTime()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 279 case ISD::SHL: in LegalizeOp()
594 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
614 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); in ExpandLoad()
772 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) in ExpandSEXTINREG()
783 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
906 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
921 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) || in ExpandBITREVERSE()
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| D | LegalizeIntegerTypes.cpp | 83 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; in PromoteIntegerResult()
635 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SHL()
843 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, in PromoteIntRes_VAARG()
918 case ISD::SHL: in PromoteIntegerOperand()
1041 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, in PromoteIntOp_BUILD_PAIR()
1393 case ISD::SHL: in ExpandIntegerResult()
1442 if (N->getOpcode() == ISD::SHL) { in ExpandShiftByConstant()
1447 Hi = DAG.getNode(ISD::SHL, DL, in ExpandShiftByConstant()
1453 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
1455 DAG.getNode(ISD::SHL, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
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| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/util/ |
| D | SyntheticAccessorFSM.java | 203 public static final int SHL = SyntheticAccessorResolver.SHL_ASSIGNMENT; field in SyntheticAccessorFSM
430 mathOp = SHL; in test()
|