| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 38 SRA = 0x37, enumerator
97 case SRA: in lanaiAluCodeToString()
115 .Case("sha", SRA) in stringToLanaiAluCode()
139 case ISD::SRA: in isdToLanaiAluCode()
140 return AluCode::SRA; in isdToLanaiAluCode()
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
140 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
153 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
180 { ISD::SRA, MVT::v16i8, 2 }, in getArithmeticInstrCost()
183 { ISD::SRA, MVT::v8i16, 2 }, in getArithmeticInstrCost()
186 { ISD::SRA, MVT::v4i32, 2 }, in getArithmeticInstrCost()
189 { ISD::SRA, MVT::v2i64, 2 }, in getArithmeticInstrCost()
193 { ISD::SRA, MVT::v32i8, 4 }, in getArithmeticInstrCost()
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); in emit_single_op()
71 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
112 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1))); in emit_single_op()
134 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
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| D | sljitNativeMIPS_32.c | 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst)); in emit_single_op()
109 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst)); in emit_single_op()
312 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG)); in emit_single_op()
336 EMIT_SHIFT(SRA, SRAV); in emit_single_op()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 45 ; Check that we use SRAK over SRA where useful.
55 ; Check that we use SRA over SRAK where possible.
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| D | shift-03.ll | 5 ; Check the low end of the SRA range.
14 ; Check the high end of the defined SRA range.
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| D | shift-10.ll | 69 ; Test that SRA gets replaced with SRL if the sign bit is the only one
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| D | shift-12.ll | 36 ; Test removal of AND mask from SRA.
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 73 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
552 return DAG.getNode(ISD::SRA, N->getDebugLoc(), in PromoteIntRes_SRA()
785 case ISD::SRA: in PromoteIntegerOperand()
1149 case ISD::SRA: in ExpandIntegerResult()
1318 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1320 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1323 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1325 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1329 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1337 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
[all …]
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| D | DAGCombiner.cpp | 837 if (Opc == ISD::SRA) in PromoteIntShiftOp()
1071 case ISD::SRA: return visitSRA(N); in visit()
1148 case ISD::SRA: in combine()
1786 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, in visitSDIV()
1798 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, in visitSDIV() local
1804 return SRA; in visitSDIV()
1806 AddToWorkList(SRA.getNode()); in visitSDIV()
1808 DAG.getConstant(0, VT), SRA); in visitSDIV()
1988 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, in visitMULHS()
2243 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && in SimplifyBinOpWithSameOpcodeHands()
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | pr14204.ll | 4 ; SLL/SRA.
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
678 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
919 case ISD::SRA: in PromoteIntegerOperand()
1394 case ISD::SRA: in ExpandIntegerResult()
1484 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1486 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1489 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1491 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1495 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1503 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
[all …]
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| D | LegalizeVectorOps.cpp | 280 case ISD::SRA: in LegalizeOp()
615 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
771 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || in ExpandSEXTINREG()
784 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); in ExpandSEXTINREG()
828 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 98 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
101 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
184 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
607 case ISD::SRA: in LowerShifts()
608 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
827 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
987 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
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| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUNodes.td | 86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
89 def SPUvec_sra: SDNode<"ISD::SRA", SPUvecshift_type, []>;
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| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator
177 case SRA: in main()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 91 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
94 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
184 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
728 case ISD::SRA: in LowerShifts()
729 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
948 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
1130 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
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| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, enumerator
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUTargetTransformInfo.cpp | 135 case ISD::SRA: { in getArithmeticInstrCost()
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| D | AMDGPUISelLowering.cpp | 372 setOperationAction(ISD::SRA, VT, Expand); in AMDGPUTargetLowering()
477 setTargetDAGCombine(ISD::SRA); in AMDGPUTargetLowering()
1264 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
1674 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
1777 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp); in LowerFROUND64()
1778 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64, in LowerFROUND64()
1931 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit); in LowerINT_TO_FP32()
2382 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
2392 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine()
2613 case ISD::SRA: { in PerformDAGCombine()
[all …]
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