1 //==-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that MSP430 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_MSP430_ISELLOWERING_H 16 #define LLVM_TARGET_MSP430_ISELLOWERING_H 17 18 #include "MSP430.h" 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/Target/TargetLowering.h" 21 22 namespace llvm { 23 namespace MSP430ISD { 24 enum { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 27 /// Return with a flag operand. Operand 0 is the chain operand. 28 RET_FLAG, 29 30 /// Same as RET_FLAG, but used for returning from ISRs. 31 RETI_FLAG, 32 33 /// Y = R{R,L}A X, rotate right (left) arithmetically 34 RRA, RLA, 35 36 /// Y = RRC X, rotate right via carry 37 RRC, 38 39 /// CALL - These operations represent an abstract call 40 /// instruction, which includes a bunch of information. 41 CALL, 42 43 /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, 44 /// and TargetGlobalAddress. 45 Wrapper, 46 47 /// CMP - Compare instruction. 48 CMP, 49 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag 51 /// operand produced by a CMP instruction. 52 SETCC, 53 54 /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1 55 /// is the block to branch if condition is true, operand 2 is the 56 /// condition code, and operand 3 is the flag operand produced by a CMP 57 /// instruction. 58 BR_CC, 59 60 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 61 /// is condition code and operand 4 is flag operand. 62 SELECT_CC, 63 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL 66 }; 67 } 68 69 class MSP430Subtarget; 70 class MSP430TargetMachine; 71 72 class MSP430TargetLowering : public TargetLowering { 73 public: 74 explicit MSP430TargetLowering(MSP430TargetMachine &TM); 75 getShiftAmountTy(EVT LHSTy)76 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 77 78 /// LowerOperation - Provide custom lowering hooks for some operations. 79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 80 81 /// getTargetNodeName - This method returns the name of a target specific 82 /// DAG node. 83 virtual const char *getTargetNodeName(unsigned Opcode) const; 84 85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; 86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 91 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 92 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; 93 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 94 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 95 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 96 97 TargetLowering::ConstraintType 98 getConstraintType(const std::string &Constraint) const; 99 std::pair<unsigned, const TargetRegisterClass*> 100 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 101 102 /// isTruncateFree - Return true if it's free to truncate a value of type 103 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in 104 /// register R15W to i8 by referencing its sub-register R15B. 105 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 106 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 107 108 /// isZExtFree - Return true if any actual instruction that defines a value 109 /// of type Ty1 implicit zero-extends the value to Ty2 in the result 110 /// register. This does not necessarily include registers defined in unknown 111 /// ways, such as incoming arguments, or copies from unknown virtual 112 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not 113 /// necessarily apply to truncate instructions. e.g. on msp430, all 114 /// instructions that define 8-bit values implicit zero-extend the result 115 /// out to 16 bits. 116 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 117 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 118 119 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI, 120 MachineBasicBlock *BB) const; 121 MachineBasicBlock* EmitShiftInstr(MachineInstr *MI, 122 MachineBasicBlock *BB) const; 123 124 private: 125 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 126 CallingConv::ID CallConv, bool isVarArg, 127 bool isTailCall, 128 const SmallVectorImpl<ISD::OutputArg> &Outs, 129 const SmallVectorImpl<SDValue> &OutVals, 130 const SmallVectorImpl<ISD::InputArg> &Ins, 131 DebugLoc dl, SelectionDAG &DAG, 132 SmallVectorImpl<SDValue> &InVals) const; 133 134 SDValue LowerCCCArguments(SDValue Chain, 135 CallingConv::ID CallConv, 136 bool isVarArg, 137 const SmallVectorImpl<ISD::InputArg> &Ins, 138 DebugLoc dl, 139 SelectionDAG &DAG, 140 SmallVectorImpl<SDValue> &InVals) const; 141 142 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 143 CallingConv::ID CallConv, bool isVarArg, 144 const SmallVectorImpl<ISD::InputArg> &Ins, 145 DebugLoc dl, SelectionDAG &DAG, 146 SmallVectorImpl<SDValue> &InVals) const; 147 148 virtual SDValue 149 LowerFormalArguments(SDValue Chain, 150 CallingConv::ID CallConv, bool isVarArg, 151 const SmallVectorImpl<ISD::InputArg> &Ins, 152 DebugLoc dl, SelectionDAG &DAG, 153 SmallVectorImpl<SDValue> &InVals) const; 154 virtual SDValue 155 LowerCall(SDValue Chain, SDValue Callee, 156 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 157 const SmallVectorImpl<ISD::OutputArg> &Outs, 158 const SmallVectorImpl<SDValue> &OutVals, 159 const SmallVectorImpl<ISD::InputArg> &Ins, 160 DebugLoc dl, SelectionDAG &DAG, 161 SmallVectorImpl<SDValue> &InVals) const; 162 163 virtual SDValue 164 LowerReturn(SDValue Chain, 165 CallingConv::ID CallConv, bool isVarArg, 166 const SmallVectorImpl<ISD::OutputArg> &Outs, 167 const SmallVectorImpl<SDValue> &OutVals, 168 DebugLoc dl, SelectionDAG &DAG) const; 169 170 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 171 SDValue &Base, 172 SDValue &Offset, 173 ISD::MemIndexedMode &AM, 174 SelectionDAG &DAG) const; 175 176 const MSP430Subtarget &Subtarget; 177 const MSP430TargetMachine &TM; 178 const TargetData *TD; 179 }; 180 } // namespace llvm 181 182 #endif // LLVM_TARGET_MSP430_ISELLOWERING_H 183