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Searched refs:SRL (Results 1 – 25 of 165) sorted by relevance

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/external/llvm/lib/Target/Lanai/
DLanaiAluCode.h37 SRL = 0x27, enumerator
95 case SRL: in lanaiAluCodeToString()
114 .Case("srl", SRL) in stringToLanaiAluCode()
137 case ISD::SRL: in isdToLanaiAluCode()
138 return AluCode::SRL; in isdToLanaiAluCode()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
139 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
152 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
158 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
179 { ISD::SRL, MVT::v16i8, 2 }, in getArithmeticInstrCost()
182 { ISD::SRL, MVT::v8i16, 2 }, in getArithmeticInstrCost()
185 { ISD::SRL, MVT::v4i32, 2 }, in getArithmeticInstrCost()
188 { ISD::SRL, MVT::v2i64, 2 }, in getArithmeticInstrCost()
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dn32.S120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
/external/libffi/src/mips/
Dn32.S120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
/external/python/cpython3/Modules/_ctypes/libffi/src/mips/
Dn32.S120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
/external/llvm/test/CodeGen/Mips/
Dfcopysign-f32-f64.ll40 ; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
41 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
/external/llvm/test/CodeGen/SystemZ/
Dshift-09.ll25 ; Check that we use SRLK over SRL where useful.
35 ; Check that we use SRL over SRLK where possible.
Dshift-02.ll5 ; Check the low end of the SRL range.
14 ; Check the high end of the defined SRL range.
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp74 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
561 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); in PromoteIntRes_SRL()
661 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
786 case ISD::SRL: in PromoteIntegerOperand()
1150 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1290 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1296 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1301 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
1309 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
[all …]
DLegalizeVectorOps.cpp156 case ISD::SRL: in LegalizeOp()
305 !TLI.isOperationLegalOrCustom(ISD::SRL, VT)) in ExpandUINT_TO_FLOAT()
325 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
DDAGCombiner.cpp839 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1072 case ISD::SRL: return visitSRL(N); in visit()
1149 case ISD::SRL: in combine()
1792 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, in visitSDIV() local
1795 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); in visitSDIV()
1796 AddToWorkList(SRL.getNode()); in visitSDIV()
1847 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, in visitUDIV()
1861 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); in visitUDIV()
2005 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2041 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
[all …]
DTargetLowering.cpp1448 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
1456 Opc = ISD::SRL; in SimplifyDemandedBits()
1499 case ISD::SRL: in SimplifyDemandedBits()
1517 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1550 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
1582 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
1729 case ISD::SRL: in SimplifyDemandedBits()
1733 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
1757 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, in SimplifyDemandedBits()
1886 if (Val.getOpcode() == ISD::SRL) in ValueHasExactlyOneBitSet()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
320 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
333 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), in PromoteIntRes_BITREVERSE()
689 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
788 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
920 case ISD::SRL: in PromoteIntegerOperand()
1395 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1457 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1463 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1467 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
[all …]
DTargetLowering.cpp671 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
679 Opc = ISD::SRL; in SimplifyDemandedBits()
719 InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
746 case ISD::SRL: in SimplifyDemandedBits()
771 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
804 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
844 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0), in SimplifyDemandedBits()
854 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
1052 case ISD::SRL: in SimplifyDemandedBits()
1056 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
[all …]
DLegalizeVectorOps.cpp281 case ISD::SRL: in LegalizeOp()
582 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
907 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) && in ExpandBITREVERSE()
922 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) || in ExpandBITREVERSE()
984 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) in ExpandUINT_TO_FLOAT()
1004 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp351 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
398 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
400 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
406 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
408 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
419 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
426 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && in SelectBitfieldInsert()
991 case ISD::SRL: { in Select()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp176 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, in addIPMSequence() local
178 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, in addIPMSequence()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h28 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUNodes.td86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
88 def SPUvec_srl: SDNode<"ISD::SRL", SPUvecshift_type, []>;
/external/valgrind/none/tests/mips64/
Dshift_instructions.c10 SRA, SRAV, SRL, SRLV enumerator
189 case SRL: in main()
/external/pcre/dist2/src/sljit/
DsljitNativeSPARC_32.c71 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()

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