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Searched refs:TRI (Results 1 – 25 of 484) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DLivePhysRegs.h44 const TargetRegisterInfo *TRI; variable
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {} in LivePhysRegs()
54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) { in LivePhysRegs() argument
55 assert(TRI && "Invalid TargetRegisterInfo pointer."); in LivePhysRegs()
56 LiveRegs.setUniverse(TRI->getNumRegs()); in LivePhysRegs()
60 void init(const TargetRegisterInfo *TRI) { in init() argument
61 assert(TRI && "Invalid TargetRegisterInfo pointer."); in init()
62 this->TRI = TRI; in init()
64 LiveRegs.setUniverse(TRI->getNumRegs()); in init()
75 assert(TRI && "LivePhysRegs is not initialized."); in addReg()
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/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { in hasVGPROperands() argument
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
130 const SIRegisterInfo &TRI, in getCopyRegClasses() argument
138 TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()
146 TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
153 const SIRegisterInfo &TRI) { in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
159 const SIRegisterInfo &TRI) { in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
177 const SIRegisterInfo *TRI, in foldVGPRCopyIntoRegSequence() argument
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DSIFrameLowering.cpp64 const SIRegisterInfo *TRI = &TII->getRegisterInfo(); in emitPrologue() local
75 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue( in emitPrologue()
80 PreloadedPrivateBufferReg = TRI->getPreloadedValue( in emitPrologue()
100 = TRI->getPreloadedValue(MF, SIRegisterInfo::FLAT_SCRATCH_INIT); in emitPrologue()
106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitPrologue()
110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitPrologue()
155 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) { in emitPrologue()
174 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) { in emitPrologue()
196 TRI->isSubRegisterEq(ScratchRsrcReg, Reg)) in emitPrologue()
209 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg)); in emitPrologue()
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DR600ExpandSpecialInstrs.cpp71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
179 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
200 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
203 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
206 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
231 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
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DSIMachineFunctionInfo.cpp149 const SIRegisterInfo &TRI) { in addPrivateSegmentBuffer() argument
150 PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
156 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) { in addDispatchPtr() argument
157 DispatchPtrUserSGPR = TRI.getMatchingSuperReg( in addDispatchPtr()
163 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) { in addQueuePtr() argument
164 QueuePtrUserSGPR = TRI.getMatchingSuperReg( in addQueuePtr()
170 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) { in addKernargSegmentPtr() argument
171 KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg( in addKernargSegmentPtr()
177 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) { in addFlatScratchInit() argument
178 FlatScratchInitUserSGPR = TRI.getMatchingSuperReg( in addFlatScratchInit()
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/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp33 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {} in RegisterClassInfo()
40 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
41 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction()
42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
43 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
50 assert(TRI && "no register info set"); in runOnMachineFunction()
51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
56 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
103 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
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DTargetRegisterInfo.cpp45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
54 else if (TRI && Reg < TRI->getNumRegs()) in PrintReg()
55 OS << '%' << TRI->getName(Reg); in PrintReg()
59 if (TRI) in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
67 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { in PrintRegUnit() argument
68 return Printable([Unit, TRI](raw_ostream &OS) { in PrintRegUnit()
70 if (!TRI) { in PrintRegUnit()
76 if (Unit >= TRI->getNumRegUnits()) { in PrintRegUnit()
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DLiveRegMatrix.cpp50 TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction()
54 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
74 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, in foreachUnit() argument
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
99 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
105 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range); in assign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
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DAggressiveAntiDepBreaker.cpp118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in AggressiveAntiDepBreaker()
123 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
133 dbgs() << " " << TRI->getName(r)); in AggressiveAntiDepBreaker()
143 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
153 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
166 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
169 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
197 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
206 dbgs() << " " << TRI->getName(Reg) << "=g" << in Observe()
243 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs()
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DRegisterScavenging.cpp35 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) { in setRegUsed()
66 TRI = MF.getSubtarget().getRegisterInfo(); in enterBasicBlock()
69 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) && in enterBasicBlock()
79 NumRegUnits = TRI->getNumRegUnits(); in enterBasicBlock()
93 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) in addRegUnits()
110 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) { in determineKillsAndDefs()
111 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) { in determineKillsAndDefs()
211 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in forward()
217 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { in forward()
236 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && in forward()
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DStackMaps.cpp78 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) { in getDwarfRegNum() argument
79 int RegNum = TRI->getDwarfRegNum(Reg, false); in getDwarfRegNum()
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR) in getDwarfRegNum()
81 RegNum = TRI->getDwarfRegNum(*SR, false); in getDwarfRegNum()
91 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); in parseOperand() local
105 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
114 getDwarfRegNum(Reg, TRI), Imm); in parseOperand()
139 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg()); in parseOperand()
143 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI); in parseOperand()
144 unsigned LLVMRegNum = TRI->getLLVMRegNum(DwarfRegNum, false); in parseOperand()
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DRegUsageInfoCollector.cpp62 void markRegClobbered(const TargetRegisterInfo *TRI, uint32_t *RegMask,
79 void RegUsageInfoCollector::markRegClobbered(const TargetRegisterInfo *TRI, in markRegClobbered() argument
82 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) in markRegClobbered()
94 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); in runOnMachineFunction() local
106 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32; in runOnMachineFunction()
117 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) in runOnMachineFunction()
119 markRegClobbered(TRI, &RegMask[0], PReg); in runOnMachineFunction()
123 TRI->getCallPreservedMask(MF, F->getCallingConv()); in runOnMachineFunction()
133 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) in runOnMachineFunction()
135 DEBUG(dbgs() << TRI->getName(PReg) << " "); in runOnMachineFunction()
DCriticalAntiDepBreaker.cpp34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI), in CriticalAntiDepBreaker()
35 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
36 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
43 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
61 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
74 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
76 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
179 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
189 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { in PrescanInstruction()
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DMachineCopyPropagation.cpp40 const TargetRegisterInfo *TRI; member in __anondf733ea70111::MachineCopyPropagation
87 const TargetRegisterInfo &TRI) { in removeRegsFromMap() argument
90 for (MCSubRegIterator SR(Reg, &TRI, true); SR.isValid(); ++SR) in removeRegsFromMap()
111 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in ClobberRegister()
117 removeRegsFromMap(AvailCopyMap, SI->second, *TRI); in ClobberRegister()
130 unsigned Def, const TargetRegisterInfo *TRI) { in isNopCopy() argument
137 if (!TRI->isSubRegister(PreviousSrc, Src)) in isNopCopy()
139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy()
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
160 if (!isNopCopy(PrevCopy, Src, Def, TRI)) in eraseIfRedundant()
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DDetectDeadLanes.cpp112 const TargetRegisterInfo *TRI; member in __anon257b486d0111::DetectDeadLanes
167 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); in isCrossCopy() local
181 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
193 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
206 UsedLanes = TRI->composeSubRegIndexLaneMask(MOSubReg, UsedLanes); in addUsedLanesOnOperand()
246 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
251 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
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/external/llvm/lib/CodeGen/AsmPrinter/
DDwarfExpression.cpp68 bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI, in AddMachineRegIndirect() argument
70 if (isFrameRegister(TRI, MachineReg)) { in AddMachineRegIndirect()
77 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegIndirect()
85 bool DwarfExpression::AddMachineRegPiece(const TargetRegisterInfo &TRI, in AddMachineRegPiece() argument
89 if (!TRI.isPhysicalRegister(MachineReg)) in AddMachineRegPiece()
92 int Reg = TRI.getDwarfRegNum(MachineReg, false); in AddMachineRegPiece()
104 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { in AddMachineRegPiece()
105 Reg = TRI.getDwarfRegNum(*SR, false); in AddMachineRegPiece()
107 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); in AddMachineRegPiece()
108 unsigned Size = TRI.getSubRegIdxSize(Idx); in AddMachineRegPiece()
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/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBank.cpp24 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
26 assert(ContainedRegClasses.size() == TRI.getNumRegClasses() && in verify()
28 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) { in verify()
29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
40 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
75 void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
76 print(dbgs(), /* IsForDebug */ true, TRI); in dump()
80 const TargetRegisterInfo *TRI) const { in print()
90 if (!TRI || ContainedRegClasses.empty()) in print()
92 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() && in print()
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DRegisterBankInfo.cpp46 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const { in verify()
52 assert(RegBank.verify(TRI) && "RegBank is invalid"); in verify()
68 const TargetRegisterInfo &TRI, in addRegBankCoverage() argument
71 unsigned NbOfRegClasses = TRI.getNumRegClasses(); in addRegBankCoverage()
78 else if (RB.covers(*TRI.getRegClass(RCId))) in addRegBankCoverage()
93 const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId); in addRegBankCoverage()
95 DEBUG(dbgs() << "Examine: " << TRI.getRegClassName(&CurRC) in addRegBankCoverage()
110 for (BitMaskClassIterator It(CurRC.getSubClassMask(), TRI); It.isValid(); in addRegBankCoverage()
116 DEBUG(dbgs() << TRI.getRegClassName(TRI.getRegClass(SubRCId)) << ", "); in addRegBankCoverage()
141 const TargetRegisterClass *SubRC = TRI.getRegClass(SubRCId); in addRegBankCoverage()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DVirtRegRewriter.cpp69 const TargetRegisterInfo &TRI) { in substitutePhysReg() argument
71 MO.substPhysReg(Reg, TRI); in substitutePhysReg()
80 MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true); in substitutePhysReg()
160 const TargetRegisterInfo *TRI; member in __anon9ff05e360311::AvailableSpills
179 : TRI(tri), TII(tii) { in AvailableSpills()
188 const TargetRegisterInfo *getRegInfo() const { return TRI; } in getRegInfo()
219 DEBUG(dbgs() << " in physreg " << TRI->getName(Reg) in addAvailable()
289 const TargetRegisterInfo *TRI, in ComputeReloadLoc() argument
327 for (const unsigned *Alias = TRI->getAliasSet(PhysReg); *Alias; ++Alias) in ComputeReloadLoc()
473 static void ResurrectConfirmedKill(unsigned Reg, const TargetRegisterInfo* TRI, in ResurrectConfirmedKill() argument
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DRegisterScavenging.cpp40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in setUsed()
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) in isAliasUsed()
83 TRI = TM.getRegisterInfo(); in enterBasicBlock()
86 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && in enterBasicBlock()
91 NumPhysRegs = TRI->getNumRegs(); in enterBasicBlock()
95 ReservedRegs = TRI->getReservedRegs(MF); in enterBasicBlock()
99 const unsigned *CSRegs = TRI->getCalleeSavedRegs(); in enterBasicBlock()
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) in addRegWithSubRegs()
119 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++) in addRegWithAliases()
202 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in forward()
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DAggressiveAntiDepBreaker.cpp123 TRI(MF.getTarget().getRegisterInfo()), in AggressiveAntiDepBreaker()
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
139 dbgs() << " " << TRI->getName(r)); in AggressiveAntiDepBreaker()
149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
160 for (const unsigned *Alias = TRI->getOverlaps(*I); in StartBlock()
176 for (const unsigned *Alias = TRI->getOverlaps(*I); in StartBlock()
189 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { in StartBlock()
192 for (const unsigned *Alias = TRI->getOverlaps(Reg); in StartBlock()
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
229 dbgs() << " " << TRI->getName(Reg) << "=g" << in Observe()
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DRegisterClassInfo.cpp27 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) in RegisterClassInfo()
35 if (MF->getTarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
36 TRI = MF->getTarget().getRegisterInfo(); in runOnMachineFunction()
37 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
42 const unsigned *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
47 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
49 for (const unsigned *AS = TRI->getOverlaps(Reg); in runOnMachineFunction()
57 BitVector RR = TRI->getReservedRegs(*MF); in runOnMachineFunction()
103 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC)) in compute()
110 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
/external/llvm/lib/Target/Mips/
DMipsOptionRecord.h45 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); in MipsRegInfoRecord()
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID)); in MipsRegInfoRecord()
53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); in MipsRegInfoRecord()
54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); in MipsRegInfoRecord()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstr.h308 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
309 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
329 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
330 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
337 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
338 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
344 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
345 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
352 const TargetRegisterInfo *TRI = NULL) const {
353 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
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/external/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp28 AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) in AArch64RegisterBankInfo() argument
34 addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI); in AArch64RegisterBankInfo()
37 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
45 addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI); in AArch64RegisterBankInfo()
48 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
50 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
57 addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI); in AArch64RegisterBankInfo()
60 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) && in AArch64RegisterBankInfo()
64 assert(verify(TRI) && "Invalid register bank information"); in AArch64RegisterBankInfo()
125 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in getInstrAlternativeMappings() local
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