/external/llvm/lib/Target/PowerPC/ |
D | PPCFastISel.cpp | 959 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local 960 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg() 962 SrcReg = TmpReg; in PPCMoveToFPReg() 1038 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local 1039 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP() 1042 SrcReg = TmpReg; in SelectIToFP() 1137 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local 1139 TII.get(TargetOpcode::COPY), TmpReg) in SelectFPToI() 1141 SrcReg = TmpReg; in SelectFPToI() 1348 unsigned TmpReg = createResultReg(RC); in processCallArgs() local [all …]
|
D | PPCFrameLowering.cpp | 1825 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local 1839 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr() 1841 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr() 1842 .addReg(TmpReg, RegState::Kill) in eliminateCallFramePseudoInstr() 1846 .addReg(TmpReg); in eliminateCallFramePseudoInstr()
|
D | PPCISelLowering.cpp | 8469 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local 8488 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary() 8490 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); in EmitAtomicBinary() 8553 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local 8611 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary() 8616 .addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary() 9270 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local 9342 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) in EmitInstrWithCustomInserter() 9345 .addReg(TmpReg).addReg(OldVal3Reg); in EmitInstrWithCustomInserter() 9372 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) in EmitInstrWithCustomInserter()
|
/external/llvm/lib/Target/Mips/AsmParser/ |
D | MipsAsmParser.cpp | 2176 unsigned TmpReg = DstReg; in loadImmediate() local 2184 TmpReg = ATReg; in loadImmediate() 2204 unsigned TmpReg = DstReg; in loadImmediate() local 2206 TmpReg = getATReg(IDLoc); in loadImmediate() 2207 if (!TmpReg) in loadImmediate() 2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate() 2213 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() 2227 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate() 2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate() 2230 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate() [all …]
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 223 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI)); in ExpandFPMLxInstruction() local 225 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() 237 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
|
D | Thumb1RegisterInfo.cpp | 655 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 659 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex() 662 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex() 666 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex() 671 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
|
/external/llvm/lib/Target/AMDGPU/ |
D | SIRegisterInfo.cpp | 518 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local 545 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex() 567 .addReg(TmpReg, RegState::Kill) // src in eliminateFrameIndex() 587 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local 615 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) in eliminateFrameIndex() 623 .addReg(TmpReg, RegState::Kill) in eliminateFrameIndex() 668 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local 670 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex() 672 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
|
D | SIFixSGPRCopies.cpp | 227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local 229 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg) in foldVGPRCopyIntoRegSequence() 232 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
|
D | SIInstrInfo.cpp | 727 MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, in calculateLDSSpillAddress() argument 813 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) in calculateLDSSpillAddress() 817 return TmpReg; in calculateLDSSpillAddress() 2681 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local 2684 BuildMI(MBB, MII, DL, get(AMDGPU::V_SUB_I32_e32), TmpReg) in lowerScalarAbs() 2690 .addReg(TmpReg); in lowerScalarAbs() 2901 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local 2904 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE() 2911 .addReg(TmpReg) in splitScalar64BitBFE()
|
D | SIInstrInfo.h | 125 RegScavenger *RS, unsigned TmpReg,
|
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
D | MipsTargetStreamer.cpp | 286 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument 309 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset() 311 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset() 313 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset() 325 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithSymOffset() argument 333 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in emitLoadWithSymOffset() 335 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithSymOffset() 337 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI); in emitLoadWithSymOffset()
|
/external/llvm/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local 293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() 305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
|
D | ThumbRegisterInfo.cpp | 570 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local 574 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex() 577 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex() 581 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex() 586 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
|
D | ARMISelLowering.cpp | 8507 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass in attachMEMCPYScratchRegs() local 8509 MIB.addReg(TmpReg, RegState::Define|RegState::Dead); in attachMEMCPYScratchRegs()
|
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCRegisterInfo.cpp | 289 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local 302 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr() 304 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr() 305 .addReg(TmpReg, RegState::Kill) in eliminateCallFramePseudoInstr() 310 .addReg(TmpReg); in eliminateCallFramePseudoInstr()
|
D | PPCFrameLowering.cpp | 664 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; in emitEpilogue() local 674 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in emitEpilogue() 676 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in emitEpilogue() 677 .addReg(TmpReg, RegState::Kill) in emitEpilogue() 682 .addReg(TmpReg); in emitEpilogue()
|
D | PPCISelLowering.cpp | 4678 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local 4698 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); in EmitAtomicBinary() 4700 .addReg(TmpReg).addReg(ptrA).addReg(ptrB); in EmitAtomicBinary() 4762 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local 4820 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg) in EmitPartwordAtomicBinary() 4825 .addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary() 5086 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local 5158 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg) in EmitInstrWithCustomInserter() 5161 .addReg(TmpReg).addReg(OldVal3Reg); in EmitInstrWithCustomInserter() 5188 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg) in EmitInstrWithCustomInserter()
|
/external/llvm/lib/Target/X86/AsmParser/ |
D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon01f3a6ab0111::X86AsmParser::IntelExprStateMachine 274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine() 385 BaseReg = TmpReg; in onPlus() 388 IndexReg = TmpReg; in onPlus() 422 BaseReg = TmpReg; in onMinus() 425 IndexReg = TmpReg; in onMinus() 455 TmpReg = Reg; in onRegister() 512 IndexReg = TmpReg; in onInteger() 601 BaseReg = TmpReg; in onRBrac() 604 IndexReg = TmpReg; in onRBrac() [all …]
|
/external/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 590 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local 599 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt() 604 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt() 605 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
|
D | MipsTargetStreamer.h | 143 int64_t Offset, unsigned TmpReg, SMLoc IDLoc,
|
D | MipsFastISel.cpp | 333 unsigned TmpReg = createResultReg(RC); in materialize32BitInt() local 334 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt() 335 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
|
/external/llvm/lib/CodeGen/ |
D | TwoAddressInstructionPass.cpp | 338 unsigned TmpReg = FromReg; in isRevCopyChain() local 340 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); in isRevCopyChain() 344 TmpReg = Def->getOperand(1).getReg(); in isRevCopyChain() 346 if (TmpReg == ToReg) in isRevCopyChain()
|
/external/llvm/lib/Target/AArch64/ |
D | AArch64FastISel.cpp | 379 unsigned TmpReg = createResultReg(RC); in materializeFP() local 380 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg) in materializeFP() 386 .addReg(TmpReg, getKillRegState(true)); in materializeFP() 4002 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local 4004 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri() 4008 Op0 = TmpReg; in emitLSL_ri() 4123 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local 4125 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri() 4129 Op0 = TmpReg; in emitLSR_ri() 4232 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local [all …]
|
/external/llvm/lib/Target/X86/ |
D | X86FastISel.cpp | 1675 unsigned TmpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local 1676 if (TmpReg == 0) in X86SelectBranch() 1998 unsigned TmpReg = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect() local 1999 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg) in X86FastEmitCMoveSelect() 2010 unsigned TmpReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local 2011 if (TmpReg == 0) in X86FastEmitCMoveSelect()
|
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelLowering.cpp | 11563 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); in EmitVAARG64WithCustomInserter() local 11566 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) in EmitVAARG64WithCustomInserter() 11571 .addReg(TmpReg) in EmitVAARG64WithCustomInserter()
|