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/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
DIdnaTest.txt426 B; a.b..-q--a-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
427 B; a.b..-q--ä-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
428 B; a.b..-q--a\u0308-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
429 B; A.B..-Q--A\u0308-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
430 B; A.B..-Q--Ä-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
431 B; A.b..-Q--Ä-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
432 B; A.b..-Q--A\u0308-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
433 B; a.b..xn---q----jra.e; [V2 V3 A4_2]; [V2 V3 A4_2]
435 B; a.-b.; [V3]; [V3]
436 B; a.b-.c; [V3]; [V3]
[all …]
/external/icu/icu4c/source/test/testdata/
DIdnaTest.txt426 B; a.b..-q--a-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
427 B; a.b..-q--ä-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
428 B; a.b..-q--a\u0308-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
429 B; A.B..-Q--A\u0308-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
430 B; A.B..-Q--Ä-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
431 B; A.b..-Q--Ä-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
432 B; A.b..-Q--A\u0308-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
433 B; a.b..xn---q----jra.e; [V2 V3 A4_2]; [V2 V3 A4_2]
435 B; a.-b.; [V3]; [V3]
436 B; a.b-.c; [V3]; [V3]
[all …]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
DIdnaTest.txt426 B; a.b..-q--a-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
427 B; a.b..-q--ä-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
428 B; a.b..-q--a\u0308-.e; [V2 V3 A4_2]; [V2 V3 A4_2]
429 B; A.B..-Q--A\u0308-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
430 B; A.B..-Q--Ä-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
431 B; A.b..-Q--Ä-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
432 B; A.b..-Q--A\u0308-.E; [V2 V3 A4_2]; [V2 V3 A4_2]
433 B; a.b..xn---q----jra.e; [V2 V3 A4_2]; [V2 V3 A4_2]
435 B; a.-b.; [V3]; [V3]
436 B; a.b-.c; [V3]; [V3]
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_calcmaxspectralline.s29 MOV V3.S[0], w11
30 MOV V3.S[1], w11
31 MOV V3.S[2], w11
32 MOV V3.S[3], w11
43 ORR V3.16B, V0.16B, V3.16B
44 ORR V3.16B, V1.16B, V3.16B
50 MOV W4, V3.S[0]
51 MOV W1, V3.S[1]
52 MOV W2, V3.S[2]
54 MOV W3, V3.S[3]
Dixheaacd_overlap_add1.s60 LD1 {V3.4S}, [X10], X12
64 SQNEG V0.4S, V3.4S
71 UZP1 V7.8H, V3.8H, V3.8H
72 UZP2 V6.8H, V3.8H, V3.8H
81 LD2 {V2.4H, V3.4H}, [X8], X12
84 REV64 V3.4H, V3.4H
101 SSHLL V27.4S, V3.4H, #0
114 UMULL V12.4S, V31.4H, V3.4H
116 SMLAL V12.4S, V30.4H, V3.4H
118 LD1 {V3.4S}, [X10], X12
[all …]
Dixheaacd_overlap_add2.s76 LD2 {V2.4H, V3.4H}, [X3], #16
79 UMLSL V23.4S, V4.4H, V3.4H
84 SMLSL V23.4S, V5.4H, V3.4H
97 LD2 {V2.4H, V3.4H}, [X3], #16
102 UMLSL V23.4S, V4.4H, V3.4H
114 SMLSL V23.4S, V5.4H, V3.4H
192 LD2 {V2.4H, V3.4H}, [X11], X12
194 REV64 V3.4H, V3.4H
198 UMULL V23.4S, V1.4H, V3.4H
201 SMLAL V23.4S, V0.4H, V3.4H
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Dixheaacd_sbr_imdct_using_fft.s110 LD2 {V2.S, V3.S}[0], [X5], X1
121 LD2 {V2.S, V3.S}[1], [X6] , X1
143 LD2 {V2.S, V3.S}[2], [X7] , X1
153 LD2 {V2.S, V3.S}[3], [X11] , X1
176 ADD V2.4S, V3.4S, V7.4S
180 SUB V6.4S, V3.4S, V7.4S
183 ADD V3.4S, V9.4S, V6.4S
295 ADD V20.4S, V3.4S, V19.4S
296 SUB V21.4S, V3.4S, V19.4S
306 ADD V3.4S, V7.4S, V13.4S
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/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Dvec_perf_shuffle.ll6 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32…
7 ret <4 x float> %V3
13 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >…
14 ret <4 x float> %V3
20 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >…
21 ret <4 x float> %V3
27 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; …
28 ret <4 x float> %V3
34 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; …
35 ret <4 x float> %V3
/external/eigen/test/
Dsmallvectors.cpp16 typedef Matrix<Scalar, 3, 1> V3; in smallVectors() typedef
24 V3 v3(x1, x2, x3); in smallVectors()
38 VERIFY_RAISES_ASSERT(V3(2, 1)) in smallVectors()
39 VERIFY_RAISES_ASSERT(V3(3, 2)) in smallVectors()
40 VERIFY_RAISES_ASSERT(V3(Scalar(3), 1)) in smallVectors()
41 VERIFY_RAISES_ASSERT(V3(3, Scalar(1))) in smallVectors()
42 VERIFY_RAISES_ASSERT(V3(Scalar(3), Scalar(1))) in smallVectors()
43 VERIFY_RAISES_ASSERT(V3(Scalar(123), Scalar(123))) in smallVectors()
/external/llvm/test/CodeGen/PowerPC/
Dvec_perf_shuffle.ll6 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32…
7 ret <4 x float> %V3
13 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 >…
14 ret <4 x float> %V3
20 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 >…
21 ret <4 x float> %V3
27 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; …
28 ret <4 x float> %V3
34 …%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; …
35 ret <4 x float> %V3
/external/libxml2/test/catalogs/
Dcatal2.sgml1 PUBLIC "-//Davenport//DTD DocBook V3.0//EN" "docbook.dtd"
3 PUBLIC "-//Davenport//ELEMENTS DocBook Information Pool V3.0//EN" "dbpool.mod"
4 …NTS DocBook Document Hierarchy V3.0//EN" "dbhier.mod"PUBLIC "-//Davenport//ENTITIES DocBook Additi…
Dwhites.script2 public "-//Davenport//DTD DocBook V3.0//EN"
4 public "-//Davenport//ENTITIES DocBook Additional General Entities V3.0//EN"
Dcatal.script2 public "-//Davenport//DTD DocBook V3.0//EN"
4 public "-//Davenport//ENTITIES DocBook Additional General Entities V3.0//EN"
/external/icu/icu4c/source/data/translit/
Dblt_blt_FONIPA.txt43 $V3 = [ꪱ ꪮ ꪺ ꪽ]; # vowels written after consonant
46 $V123 = [$V12 $V3];
61 $LO $W? {($V3 $CHK)} → $1 ˧˥; # Tone class 2: High-rising tone
63 $HI $W? {($V3 $CHK)} → $1 ˦; # Tone class 5: High-mid tone
65 # after the consonant (V3).
67 $LO $W? { \uAABF ($V3 $F?)} → $1 ˧˥; # Tone class 2: High-rising tone
68 $LO $W? { \uAAC1 ($V3 $F?)} → $1 ˨˩; # Tone class 3: Low-falling tone
69 $HI $W? { \uAABF ($V3 $F?)} → $1 ˦; # Tone class 5: High-mid tone
70 $HI $W? { \uAAC1 ($V3 $F?)} → $1 ˧˩; # Tone class 6: Mid-falling tone
/external/eigen/unsupported/Eigen/CXX11/src/Tensor/
DTensorDimensions.h154 template <std::size_t V1=0, std::size_t V2=0, std::size_t V3=0, std::size_t V4=0, std::size_t V5=0>…
155 …o_size<V1>::type, typename non_zero_size<V2>::type, typename non_zero_size<V3>::type, typename non…
224 template <std::size_t V1, std::size_t V2, std::size_t V3, std::size_t V4, std::size_t V5>
225 EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::size_t array_prod(const Sizes<V1, V2, V3, V4, V5>&) {
226 return Sizes<V1, V2, V3, V4, V5>::total_size;
385 …size_t V1, std::size_t V2, std::size_t V3, std::size_t V4, std::size_t V5> struct array_size<const…
386 static const size_t value = Sizes<V1,V2,V3,V4,V5>::count;
388 …d::size_t V1, std::size_t V2, std::size_t V3, std::size_t V4, std::size_t V5> struct array_size<Si…
389 static const size_t value = Sizes<V1,V2,V3,V4,V5>::count;
391 …t V2, std::size_t V3, std::size_t V4, std::size_t V5> EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE std::s…
[all …]
/external/llvm/test/Transforms/InstCombine/
Dapint-shl-trunc.ll7 ; CHECK: %[[V3:.*]] = icmp ne i39 %[[V2]], 0
8 ; CHECK: ret i1 %[[V3]]
19 ; CHECK: %[[V3:.*]] = icmp ne i799 %[[V2]], 0
20 ; CHECK: ret i1 %[[V3]]
/external/clang/test/CodeGenCXX/
Dvtt-layout.cpp32 class V3 {virtual void g(); }; class
34 class C2 : public virtual V3, virtual V2 { int i; };
51 class V3 {virtual void g(); }; class
53 class C2 : public virtual V3, virtual V2 { int i; };
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormats.td207 // LD Instruction Class in V2/V3/V4.
223 // LD Instruction Class in V2/V3/V4.
239 // ST Instruction Class in V2/V3 can take SLOT0 only.
241 // Definition of the instruction class CHANGED from V2/V3 to V4.
262 // ST Instruction Class in V2/V3 can take SLOT0 only.
264 // Definition of the instruction class CHANGED from V2/V3 to V4.
270 // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
276 // ALU32 Instruction Class in V2/V3/V4.
282 // ALU64 Instruction Class in V2/V3.
285 // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
[all …]
/external/llvm/unittests/Support/
DAlignOfTest.cpp64 struct V3 : V1 { struct
65 ~V3() override;
70 struct V5 : V4, V3 { double z;
85 V3::~V3() {} in ~V3()
147 [AlignOf<V3>::Alignment > 0]
187 EXPECT_LE(alignOf<V1>(), alignOf<V3>()); in TEST()
269 EXPECT_EQ(alignOf<V3>(), alignOf<AlignedCharArrayUnion<V3> >()); in TEST()
334 EXPECT_EQ(sizeof(V3), sizeof(AlignedCharArrayUnion<V3>)); in TEST()
/external/clang/test/CodeGen/
Dsse41-builtins.c29 __m128i test_mm_blendv_epi8(__m128i V1, __m128i V2, __m128i V3) { in test_mm_blendv_epi8() argument
32 return _mm_blendv_epi8(V1, V2, V3); in test_mm_blendv_epi8()
35 __m128d test_mm_blendv_pd(__m128d V1, __m128d V2, __m128d V3) { in test_mm_blendv_pd() argument
38 return _mm_blendv_pd(V1, V2, V3); in test_mm_blendv_pd()
41 __m128 test_mm_blendv_ps(__m128 V1, __m128 V2, __m128 V3) { in test_mm_blendv_ps() argument
44 return _mm_blendv_ps(V1, V2, V3); in test_mm_blendv_ps()
/external/antlr/antlr-3.4/runtime/Python/
DREADME17 WARNING: Currently the runtime library for V3.1 is not compatible with
18 recognizers generated by ANTLR V3.0.x. If you are an application developer,
22 It is still undetermined, if a future release of the V3.1 runtime will be
23 compatible with V3.0.x recognizers or if future runtimes V3.2+ will be
24 compatible with V3.1 recognizers.
/external/llvm/test/DebugInfo/Generic/
Drestrict.ll4 …=obj < %s | llvm-dwarfdump -debug-dump=info - | FileCheck --check-prefix=CHECK --check-prefix=V3 %s
8 ; V3: DW_AT_type {{.*}} {[[RESTRICT:0x.*]]}
9 ; V3: [[RESTRICT]]: {{.*}}DW_TAG_restrict_type
10 ; V3-NEXT: DW_AT_type {{.*}} {[[PTR:0x.*]]}
/external/llvm/test/Transforms/SimplifyCFG/
DPhiEliminate2.ll6 define i32 @FoldTwoEntryPHINode(i1 %C, i32 %V1, i32 %V2, i16 %V3) {
13 %V5 = sext i16 %V3 to i32
22 ; CHECK-NEXT: %V5 = sext i16 %V3 to i32
/external/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td620 bits<5> V3;
626 let Inst{35-32} = V3{3-0};
630 let Inst{10} = V3{4};
642 bits<5> V3;
649 let Inst{31-28} = V3{3-0};
655 let Inst{9} = V3{4};
723 bits<5> V3;
730 let Inst{31-28} = V3{3-0};
740 let Inst{9} = V3{4};
752 bits<5> V3;
[all …]
/external/selinux/scripts/
DLindent6 V3=`echo $RES | cut -d' ' -f3 | cut -d'.' -f3`
13 if [ $V3 -ge 10 ]; then

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