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Searched refs:depth_irb (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c242 struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); in brw_workaround_depthstencil_alignment() local
251 if (depth_irb) in brw_workaround_depthstencil_alignment()
252 depth_mt = depth_irb->mt; in brw_workaround_depthstencil_alignment()
263 if (depth_irb) in brw_workaround_depthstencil_alignment()
284 if (depth_irb && invalidate_depth && in brw_workaround_depthstencil_alignment()
287 invalidate_depth = invalidate_stencil && depth_irb && stencil_irb in brw_workaround_depthstencil_alignment()
288 && depth_irb->mt == stencil_irb->mt; in brw_workaround_depthstencil_alignment()
293 depth_mt ? depth_irb->mt_level : 0, in brw_workaround_depthstencil_alignment()
294 depth_mt ? depth_irb->mt_layer : 0, in brw_workaround_depthstencil_alignment()
298 if (depth_irb) { in brw_workaround_depthstencil_alignment()
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Dbrw_clear.c106 struct intel_renderbuffer *depth_irb = in brw_fast_clear_depth() local
108 struct intel_mipmap_tree *mt = depth_irb->mt; in brw_fast_clear_depth()
114 if (!intel_renderbuffer_has_hiz(depth_irb)) in brw_fast_clear_depth()
158 depth_irb->mt_level - mt->first_level) % 16) != 0) in brw_fast_clear_depth()
220 for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) { in brw_fast_clear_depth()
221 intel_hiz_exec(brw, mt, depth_irb->mt_level, in brw_fast_clear_depth()
222 depth_irb->mt_layer + layer, in brw_fast_clear_depth()
226 intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, in brw_fast_clear_depth()
Dgen6_depthstencil.c39 struct intel_renderbuffer *depth_irb; in gen6_upload_depth_stencil_state() local
42 depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); in gen6_upload_depth_stencil_state()
83 if (ctx->Depth.Test && depth_irb) { in gen6_upload_depth_stencil_state()
Dgen8_depth_state.c243 struct intel_renderbuffer *depth_irb = in pma_fix_enable() local
256 const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb); in pma_fix_enable()
277 const bool depth_test_enabled = depth_irb && ctx->Depth.Test; in pma_fix_enable()
Dgen8_wm_depth_stencil.c38 struct intel_renderbuffer *depth_irb = in gen8_upload_wm_depth_stencil() local
88 if (ctx->Depth.Test && depth_irb) { in gen8_upload_wm_depth_stencil()
Dbrw_draw.c364 struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); in brw_postdraw_set_buffers_need_resolve() local
375 if (depth_irb && brw_depth_writes_enabled(brw)) { in brw_postdraw_set_buffers_need_resolve()
377 brw_render_cache_set_add_bo(brw, depth_irb->mt->bo); in brw_postdraw_set_buffers_need_resolve()
Dbrw_context.c231 struct intel_renderbuffer *depth_irb; in intel_update_state() local
242 depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); in intel_update_state()
243 if (depth_irb) in intel_update_state()
244 intel_renderbuffer_resolve_hiz(brw, depth_irb); in intel_update_state()