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Searched refs:dl (Results 1 – 25 of 1075) sorted by relevance

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/external/iproute2/devlink/
Ddevlink.c203 struct dl { struct
222 static int dl_argc(struct dl *dl) in dl_argc() argument
224 return dl->argc; in dl_argc()
227 static char *dl_argv(struct dl *dl) in dl_argv() argument
229 if (dl_argc(dl) == 0) in dl_argv()
231 return *dl->argv; in dl_argv()
234 static void dl_arg_inc(struct dl *dl) in dl_arg_inc() argument
236 if (dl_argc(dl) == 0) in dl_arg_inc()
238 dl->argc--; in dl_arg_inc()
239 dl->argv++; in dl_arg_inc()
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/external/boringssl/src/third_party/android-cmake/
Dndk_links.md4 * http://dl.google.com/android/ndk/android-ndk-1.5_r1-windows.zip
5 * http://dl.google.com/android/ndk/android-ndk-1.5_r1-darwin-x86.zip
6 * http://dl.google.com/android/ndk/android-ndk-1.5_r1-linux-x86.zip
10 * http://dl.google.com/android/ndk/android-ndk-1.6_r1-windows.zip
11 * http://dl.google.com/android/ndk/android-ndk-1.6_r1-darwin-x86.zip
12 * http://dl.google.com/android/ndk/android-ndk-1.6_r1-linux-x86.zip
16 * http://dl.google.com/android/ndk/android-ndk-r3-windows.zip
17 * http://dl.google.com/android/ndk/android-ndk-r3-darwin-x86.zip
18 * http://dl.google.com/android/ndk/android-ndk-r3-linux-x86.zip
22 * http://dl.google.com/android/ndk/android-ndk-r4-windows.zip
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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp97 const SDLoc &dl);
99 const SDLoc &dl);
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
110 bool &NeedInvert, const SDLoc &dl);
114 unsigned NumOps, bool isSigned, const SDLoc &dl);
132 const SDLoc &dl);
144 const SDLoc &dl);
146 const SDLoc &dl);
148 const SDLoc &dl);
150 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
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DLegalizeIntegerTypes.cpp255 SDLoc dl(N); in PromoteIntRes_BITCAST() local
263 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
267 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
271 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp); in PromoteIntRes_BITCAST()
280 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
294 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
298 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
305 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
308 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
316 SDLoc dl(N); in PromoteIntRes_BSWAP() local
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DLegalizeTypesGeneric.cpp46 SDLoc dl(N); in ExpandRes_BITCAST() local
63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
97 std::tie(Lo, Hi) = DAG.SplitVector(InOp, dl, LoVT, HiVT); in ExpandRes_BITCAST()
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DTargetLowering.cpp119 const SDLoc &dl, bool doesNotReturn, in makeLibCall() argument
141 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) in makeLibCall()
153 const SDLoc &dl) const { in softenSetCCOperands()
256 dl).first; in softenSetCCOperands()
257 NewRHS = DAG.getConstant(0, dl, RetVT); in softenSetCCOperands()
265 ISD::SETCC, dl, in softenSetCCOperands()
269 dl).first; in softenSetCCOperands()
271 ISD::SETCC, dl, in softenSetCCOperands()
274 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS); in softenSetCCOperands()
342 SDLoc dl(Op); in ShrinkDemandedConstant() local
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp98 SDValue Idx, DebugLoc dl);
100 SDValue Idx, DebugLoc dl);
106 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
114 DebugLoc dl);
118 unsigned NumOps, bool isSigned, DebugLoc dl);
133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
140 DebugLoc dl);
142 DebugLoc dl);
144 DebugLoc dl);
146 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
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DLegalizeTypesGeneric.cpp45 DebugLoc dl = N->getDebugLoc(); in ExpandRes_BITCAST() local
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
85 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, in ExpandRes_BITCAST()
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DLegalizeIntegerTypes.cpp211 DebugLoc dl = N->getDebugLoc(); in PromoteIntRes_BITCAST() local
222 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); in PromoteIntRes_BITCAST()
226 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
233 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
247 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
251 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
256 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); in PromoteIntRes_BITCAST()
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
267 DebugLoc dl = N->getDebugLoc(); in PromoteIntRes_BSWAP() local
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp288 DebugLoc dl = ADDENode->getDebugLoc(); in SelectMadd() local
293 SDValue MAdd = CurDAG->getNode(MultOpc, dl, in SelectMadd()
301 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, in SelectMadd()
303 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, in SelectMadd()
362 DebugLoc dl = SUBENode->getDebugLoc(); in SelectMsub() local
367 SDValue MSub = CurDAG->getNode(MultOpc, dl, in SelectMsub()
375 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, in SelectMsub()
377 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, in SelectMsub()
426 DebugLoc dl = N->getDebugLoc(); in PerformDivRemCombine() local
428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, in PerformDivRemCombine()
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp199 DebugLoc dl = Op.getDebugLoc(); in LowerJumpTable() local
201 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI, in LowerJumpTable()
203 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi); in LowerJumpTable()
235 DebugLoc dl, SelectionDAG &DAG, in LowerCall() argument
268 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
271 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
274 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
286 StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64); in LowerCall()
288 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), in LowerCall()
292 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, in LowerCall()
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/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp48 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemset() argument
88 CLI.setDebugLoc(dl).setChain(Chain) in EmitTargetCodeForMemset()
133 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
139 Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl); in EmitTargetCodeForMemset()
143 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
148 Count = DAG.getIntPtrConstant(SizeVal, dl); in EmitTargetCodeForMemset()
149 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); in EmitTargetCodeForMemset()
153 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
156 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
162 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops); in EmitTargetCodeForMemset()
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp558 DebugLoc dl = Op.getDebugLoc(); in LowerLOAD() local
598 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, in LowerLOAD()
618 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, in LowerLOAD()
637 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); in LowerLOAD()
638 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); in LowerLOAD()
639 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); in LowerLOAD()
643 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1); in LowerLOAD()
646 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, in LowerLOAD()
653 rotate = DAG.getNode(ISD::ADD, dl, PtrVT, in LowerLOAD()
659 SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr, in LowerLOAD()
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DSPUISelDAGToDAG.cpp114 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) { in getCarryGenerateShufMask() argument
124 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getCarryGenerateShufMask()
129 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) { in getBorrowGenerateShufMask() argument
139 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getBorrowGenerateShufMask()
181 DebugLoc dl = bvNode->getDebugLoc(); in emitBuildVector() local
216 HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl, in emitBuildVector()
240 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
243 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
622 DebugLoc dl = N->getDebugLoc(); in Select() local
640 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl, in Select()
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcISelLowering.cpp85 DebugLoc dl, SelectionDAG &DAG) const { in LowerReturn() argument
114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); in LowerReturn()
129 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); in LowerReturn()
139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn()
141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, in LowerReturn()
153 DebugLoc dl, SelectionDAG &DAG, in LowerFormalArguments() argument
176 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments()
188 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); in LowerFormalArguments()
198 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, in LowerFormalArguments()
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/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp94 inline SDValue getI32Imm(unsigned Imm, const SDLoc &dl) { in getI32Imm() argument
95 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); in getI32Imm()
100 inline SDValue getI64Imm(uint64_t Imm, const SDLoc &dl) { in getI64Imm() argument
101 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); in getI64Imm()
105 inline SDValue getSmallIPtrImm(unsigned Imm, const SDLoc &dl) { in getSmallIPtrImm() argument
107 Imm, dl, PPCLowering->getPointerTy(CurDAG->getDataLayout())); in getSmallIPtrImm()
131 const SDLoc &dl);
203 SDLoc dl(Op); in SelectInlineAsmMemoryOperand() local
204 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); in SelectInlineAsmMemoryOperand()
207 dl, Op.getValueType(), in SelectInlineAsmMemoryOperand()
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DPPCISelLowering.cpp1851 SDLoc dl(N); in SelectAddressRegImm() local
1860 Disp = DAG.getTargetConstant(imm, dl, N.getValueType()); in SelectAddressRegImm()
1900 Disp = DAG.getTargetConstant(imm, dl, N.getValueType()); in SelectAddressRegImm()
1911 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0)); in SelectAddressRegImm()
1924 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
1926 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl, in SelectAddressRegImm()
1929 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); in SelectAddressRegImm()
1934 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout())); in SelectAddressRegImm()
2114 static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit, in getTOCEntry() argument
2118 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT); in getTOCEntry()
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp255 SDLoc dl(GA); in getGlobalAddressWrapper() local
258 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
263 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
265 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
330 SDLoc dl(CP); in LowerConstantPool() local
340 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); in LowerConstantPool()
353 SDLoc dl(Op); in LowerBR_JT() local
362 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); in LowerBR_JT()
365 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, in LowerBR_JT()
366 DAG.getConstant(1, dl, MVT::i32)); in LowerBR_JT()
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp216 DebugLoc dl = Op.getDebugLoc(); in LowerSELECT_CC() local
217 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), in LowerSELECT_CC()
219 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), in LowerSELECT_CC()
228 DebugLoc dl = GA.getDebugLoc(); in getGlobalAddressWrapper() local
230 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
240 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
242 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); in getGlobalAddressWrapper()
253 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) { in BuildGetId() argument
254 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in BuildGetId()
267 DebugLoc dl = Op.getDebugLoc(); in LowerGlobalTLSAddress() local
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp854 DebugLoc dl = N.getDebugLoc(); in SelectAddressRegImm() local
923 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0); in SelectAddressRegImm()
970 DebugLoc dl = N.getDebugLoc(); in SelectAddressRegImmShift() local
1037 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0); in SelectAddressRegImmShift()
1232 DebugLoc dl = Op.getDebugLoc(); in LowerSETCC() local
1243 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); in LowerSETCC()
1246 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); in LowerSETCC()
1247 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, in LowerSETCC()
1249 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); in LowerSETCC()
1266 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), in LowerSETCC()
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/external/elfutils/libelf/
Delf32_updatefile.c326 Elf_Data_List *dl = &scn->data_list; in __elfw2() local
332 assert (dl->data.d.d_off >= 0); in __elfw2()
333 assert ((GElf_Off) dl->data.d.d_off <= shdr->sh_size); in __elfw2()
334 assert (dl->data.d.d_size <= (shdr->sh_size in __elfw2()
335 - (GElf_Off) dl->data.d.d_off)); in __elfw2()
338 if (scn_start + dl->data.d.d_off > last_position in __elfw2()
339 && (dl->data.d.d_off == 0 in __elfw2()
340 || ((scn->flags | dl->flags | elf->flags) in __elfw2()
343 fill_mmap (dl->data.d.d_off, last_position, scn_start, in __elfw2()
345 last_position = scn_start + dl->data.d.d_off; in __elfw2()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp1105 DebugLoc dl, SelectionDAG &DAG, in LowerCallResult() argument
1123 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1128 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1132 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1135 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1140 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1144 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1147 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1447 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult() argument
1475 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1480 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1486 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1489 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1490 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1491 DAG.getConstant(0, dl, MVT::i32)); in LowerCallResult()
1494 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1498 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1503 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
[all …]
DARMSelectionDAGInfo.cpp25 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, in EmitSpecializedLibcall() argument
92 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src); in EmitSpecializedLibcall()
94 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitSpecializedLibcall()
115 CLI.setDebugLoc(dl) in EmitSpecializedLibcall()
129 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, in EmitTargetCodeForMemcpy() argument
142 return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align, in EmitTargetCodeForMemcpy()
146 return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align, in EmitTargetCodeForMemcpy()
186 Dst = DAG.getNode(ARMISD::MEMCPY, dl, VTs, Chain, Dst, Src, in EmitTargetCodeForMemcpy()
187 DAG.getConstant(NumRegs, dl, MVT::i32)); in EmitTargetCodeForMemcpy()
212 Loads[i] = DAG.getLoad(VT, dl, Chain, in EmitTargetCodeForMemcpy()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp363 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments() argument
371 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); in LowerFormalArguments()
383 SDLoc &dl = CLI.DL; in LowerCall() local
402 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
413 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCArguments() argument
449 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
462 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerCCCArguments()
492 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
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