Home
last modified time | relevance | path

Searched refs:inst (Results 1 – 25 of 692) sorted by relevance

12345678910>>...28

/external/webrtc/webrtc/modules/audio_processing/ns/
Dnsx_core.c303 static void UpdateNoiseEstimate(NoiseSuppressionFixedC* inst, int offset) { in UpdateNoiseEstimate() argument
311 tmp16 = WebRtcSpl_MaxValueW16(inst->noiseEstLogQuantile + offset, in UpdateNoiseEstimate()
312 inst->magnLen); in UpdateNoiseEstimate()
314 inst->qNoise = 14 - (int) WEBRTC_SPL_MUL_16_16_RSFT_WITH_ROUND( in UpdateNoiseEstimate()
316 for (i = 0; i < inst->magnLen; i++) { in UpdateNoiseEstimate()
319 tmp32no2 = kExp2Const * inst->noiseEstLogQuantile[offset + i]; in UpdateNoiseEstimate()
323 tmp16 += (int16_t) inst->qNoise; //shift to get result in Q(qNoise) in UpdateNoiseEstimate()
329 inst->noiseEstQuantile[i] = WebRtcSpl_SatW32ToW16(tmp32no1); in UpdateNoiseEstimate()
334 static void NoiseEstimationC(NoiseSuppressionFixedC* inst, in NoiseEstimationC() argument
346 tabind = inst->stages - inst->normData; in NoiseEstimationC()
[all …]
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_program_alu.c197 static int is_dst_safe_to_reuse(struct rc_instruction *inst) in is_dst_safe_to_reuse() argument
199 const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode); in is_dst_safe_to_reuse()
204 if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY) in is_dst_safe_to_reuse()
208 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY && in is_dst_safe_to_reuse()
209 inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index) in is_dst_safe_to_reuse()
217 struct rc_instruction *inst) in try_to_reuse_dst() argument
221 if (is_dst_safe_to_reuse(inst)) in try_to_reuse_dst()
222 tmp = inst->U.I.DstReg.Index; in try_to_reuse_dst()
226 return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask); in try_to_reuse_dst()
230 struct rc_instruction* inst) in transform_ABS() argument
[all …]
Dr500_fragprog.c65 struct rc_instruction * inst; in r500_transform_IF() local
85 for (inst = writer->Inst; inst != inst_if; inst = inst->Next) { in r500_transform_IF()
87 rc_get_opcode_info(inst->U.I.Opcode); in r500_transform_IF()
374 uint32_t inst; in r500FragmentProgramDump() local
380 inst0 = inst = code->inst[n].inst0; in r500FragmentProgramDump()
381 fprintf(stderr,"%d\t0:CMN_INST 0x%08x:", n, inst); in r500FragmentProgramDump()
382 switch(inst & 0x3) { in r500FragmentProgramDump()
389 inst & R500_INST_TEX_SEM_WAIT ? "TEX_WAIT" : "", in r500FragmentProgramDump()
390 inst & R500_INST_LAST ? "LAST" : "", in r500FragmentProgramDump()
391 inst & R500_INST_NOP ? "NOP" : "", in r500FragmentProgramDump()
[all …]
Dr500_fragprog_emit.c159 static unsigned int translate_arg_rgb(struct rc_pair_instruction *inst, int arg) in translate_arg_rgb() argument
161 unsigned int t = inst->RGB.Arg[arg].Source; in translate_arg_rgb()
163 t |= inst->RGB.Arg[arg].Negate << 11; in translate_arg_rgb()
164 t |= inst->RGB.Arg[arg].Abs << 12; in translate_arg_rgb()
167 t |= fix_hw_swizzle(GET_SWZ(inst->RGB.Arg[arg].Swizzle, comp)) << (3*comp + 2); in translate_arg_rgb()
172 static unsigned int translate_arg_alpha(struct rc_pair_instruction *inst, int i) in translate_arg_alpha() argument
174 unsigned int t = inst->Alpha.Arg[i].Source; in translate_arg_alpha()
175 t |= fix_hw_swizzle(GET_SWZ(inst->Alpha.Arg[i].Swizzle, 0)) << 2; in translate_arg_alpha()
176 t |= inst->Alpha.Arg[i].Negate << 5; in translate_arg_alpha()
177 t |= inst->Alpha.Arg[i].Abs << 6; in translate_arg_alpha()
[all …]
Dradeon_pair_translate.c38 static void final_rewrite(struct rc_sub_instruction *inst) in final_rewrite() argument
42 switch(inst->Opcode) { in final_rewrite()
44 inst->SrcReg[2] = inst->SrcReg[1]; in final_rewrite()
45 inst->SrcReg[1].File = RC_FILE_NONE; in final_rewrite()
46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111; in final_rewrite()
47 inst->SrcReg[1].Negate = RC_MASK_NONE; in final_rewrite()
48 inst->Opcode = RC_OPCODE_MAD; in final_rewrite()
51 tmp = inst->SrcReg[2]; in final_rewrite()
52 inst->SrcReg[2] = inst->SrcReg[0]; in final_rewrite()
53 inst->SrcReg[0] = tmp; in final_rewrite()
[all …]
Dradeon_program_print.c198 struct rc_presub_instruction inst) in rc_print_presub_instruction() argument
201 switch(inst.Opcode){ in rc_print_presub_instruction()
204 rc_print_register(f, inst.SrcReg[0].File, in rc_print_presub_instruction()
205 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); in rc_print_presub_instruction()
208 rc_print_register(f, inst.SrcReg[1].File, in rc_print_presub_instruction()
209 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); in rc_print_presub_instruction()
211 rc_print_register(f, inst.SrcReg[0].File, in rc_print_presub_instruction()
212 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr); in rc_print_presub_instruction()
215 rc_print_register(f, inst.SrcReg[1].File, in rc_print_presub_instruction()
216 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr); in rc_print_presub_instruction()
[all …]
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_opt_algebraic.c41 dump_from(struct vc4_compile *c, struct qinst *inst) in dump_from() argument
47 qir_dump_inst(c, inst); in dump_from()
52 dump_to(struct vc4_compile *c, struct qinst *inst) in dump_to() argument
58 qir_dump_inst(c, inst); in dump_to()
94 replace_with_mov(struct vc4_compile *c, struct qinst *inst, struct qreg arg) in replace_with_mov() argument
96 dump_from(c, inst); in replace_with_mov()
98 inst->src[0] = arg; in replace_with_mov()
99 if (qir_has_implicit_tex_uniform(inst)) in replace_with_mov()
100 inst->src[1] = inst->src[qir_get_tex_uniform_src(inst)]; in replace_with_mov()
102 if (qir_is_mul(inst)) in replace_with_mov()
[all …]
Dvc4_qpu.c33 set_src_raddr(uint64_t inst, struct qpu_reg src) in set_src_raddr() argument
36 assert(QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_NOP || in set_src_raddr()
37 QPU_GET_FIELD(inst, QPU_RADDR_A) == src.addr); in set_src_raddr()
38 return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_A); in set_src_raddr()
42 assert((QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_NOP || in set_src_raddr()
43 QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr) && in set_src_raddr()
44 QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM); in set_src_raddr()
45 return QPU_UPDATE_FIELD(inst, src.addr, QPU_RADDR_B); in set_src_raddr()
49 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_SMALL_IMM) { in set_src_raddr()
50 assert(QPU_GET_FIELD(inst, QPU_RADDR_B) == src.addr); in set_src_raddr()
[all …]
Dvc4_qpu_validate.c28 fail_instr(uint64_t inst, const char *msg) in fail_instr() argument
31 vc4_qpu_disasm(&inst, 1); in fail_instr()
37 writes_reg(uint64_t inst, uint32_t w) in writes_reg() argument
39 return (QPU_GET_FIELD(inst, QPU_WADDR_ADD) == w || in writes_reg()
40 QPU_GET_FIELD(inst, QPU_WADDR_MUL) == w); in writes_reg()
44 _reads_reg(uint64_t inst, uint32_t r, bool ignore_a, bool ignore_b) in _reads_reg() argument
49 { QPU_GET_FIELD(inst, QPU_ADD_A) }, in _reads_reg()
50 { QPU_GET_FIELD(inst, QPU_ADD_B) }, in _reads_reg()
51 { QPU_GET_FIELD(inst, QPU_MUL_A) }, in _reads_reg()
52 { QPU_GET_FIELD(inst, QPU_MUL_B) }, in _reads_reg()
[all …]
/external/mesa3d/src/gallium/drivers/ilo/shader/
Dtoy_compiler_disasm.c203 disasm_inst_decode_dw0_opcode_gen6(struct disasm_inst *inst, uint32_t dw0) in disasm_inst_decode_dw0_opcode_gen6() argument
205 ILO_DEV_ASSERT(inst->dev, 6, 8); in disasm_inst_decode_dw0_opcode_gen6()
207 inst->opcode = GEN_EXTRACT(dw0, GEN6_INST_OPCODE); in disasm_inst_decode_dw0_opcode_gen6()
209 switch (inst->opcode) { in disasm_inst_decode_dw0_opcode_gen6()
211 inst->has_jip = true; in disasm_inst_decode_dw0_opcode_gen6()
212 inst->has_uip = (ilo_dev_gen(inst->dev) >= ILO_GEN(7)); in disasm_inst_decode_dw0_opcode_gen6()
215 inst->has_jip = true; in disasm_inst_decode_dw0_opcode_gen6()
216 inst->has_uip = (ilo_dev_gen(inst->dev) >= ILO_GEN(8)); in disasm_inst_decode_dw0_opcode_gen6()
221 inst->has_uip = true; in disasm_inst_decode_dw0_opcode_gen6()
232 inst->has_jip = true; in disasm_inst_decode_dw0_opcode_gen6()
[all …]
Dtoy_legalize.c38 toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst, in toy_compiler_lower_to_send() argument
41 assert(inst->opcode >= 128); in toy_compiler_lower_to_send()
43 inst->opcode = (sendc) ? GEN6_OPCODE_SENDC : GEN6_OPCODE_SEND; in toy_compiler_lower_to_send()
46 assert(inst->thread_ctrl == 0); in toy_compiler_lower_to_send()
48 assert(inst->cond_modifier == GEN6_COND_NONE); in toy_compiler_lower_to_send()
49 inst->cond_modifier = sfid; in toy_compiler_lower_to_send()
77 toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst) in toy_compiler_lower_math() argument
83 for (i = 0; i < ARRAY_SIZE(inst->src); i++) { in toy_compiler_lower_math()
84 if (tsrc_is_null(inst->src[i])) in toy_compiler_lower_math()
89 if (toy_file_is_virtual(inst->src[i].file) && in toy_compiler_lower_math()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4_copy_propagation.cpp44 is_direct_copy(vec4_instruction *inst) in is_direct_copy() argument
46 return (inst->opcode == BRW_OPCODE_MOV && in is_direct_copy()
47 !inst->predicate && in is_direct_copy()
48 inst->dst.file == VGRF && in is_direct_copy()
49 inst->dst.offset % REG_SIZE == 0 && in is_direct_copy()
50 !inst->dst.reladdr && in is_direct_copy()
51 !inst->src[0].reladdr && in is_direct_copy()
52 (inst->dst.type == inst->src[0].type || in is_direct_copy()
53 (inst->dst.type == BRW_REGISTER_TYPE_F && in is_direct_copy()
54 inst->src[0].type == BRW_REGISTER_TYPE_VF))); in is_direct_copy()
[all …]
Dbrw_vec4.cpp312 vec4_visitor::implied_mrf_writes(vec4_instruction *inst) in implied_mrf_writes() argument
314 if (inst->mlen == 0 || inst->is_send_from_grf()) in implied_mrf_writes()
317 switch (inst->opcode) { in implied_mrf_writes()
361 return inst->header_size; in implied_mrf_writes()
389 foreach_inst_in_block_safe(vec4_instruction, inst, block) { in opt_vector_float()
398 if (inst->opcode == BRW_OPCODE_MOV && in opt_vector_float()
399 inst->src[0].file == IMM && in opt_vector_float()
400 inst->predicate == BRW_PREDICATE_NONE && in opt_vector_float()
401 inst->dst.writemask != WRITEMASK_XYZW && in opt_vector_float()
402 type_sz(inst->src[0].type) < 8 && in opt_vector_float()
[all …]
Dbrw_disasm.c735 dest(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst) in dest() argument
739 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) { in dest()
740 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) { in dest()
741 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst), in dest()
742 brw_inst_dst_da_reg_nr(devinfo, inst)); in dest()
745 if (brw_inst_dst_da1_subreg_nr(devinfo, inst)) in dest()
746 format(file, ".%"PRIu64, brw_inst_dst_da1_subreg_nr(devinfo, inst) / in dest()
747 reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]); in dest()
750 brw_inst_dst_hstride(devinfo, inst), NULL); in dest()
753 brw_inst_dst_reg_type(devinfo, inst), NULL); in dest()
[all …]
Dbrw_fs.cpp48 const fs_inst *inst);
192 fs_inst *inst = bld.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, in VARYING_PULL_CONSTANT_LOAD() local
194 inst->size_written = 4 * vec4_result.component_size(inst->exec_size); in VARYING_PULL_CONSTANT_LOAD()
223 fs_inst::equals(fs_inst *inst) const in equals()
225 return (opcode == inst->opcode && in equals()
226 dst.equals(inst->dst) && in equals()
227 src[0].equals(inst->src[0]) && in equals()
228 src[1].equals(inst->src[1]) && in equals()
229 src[2].equals(inst->src[2]) && in equals()
230 saturate == inst->saturate && in equals()
[all …]
Dbrw_schedule_instructions.cpp65 schedule_node(backend_instruction *inst, instruction_scheduler *sched);
69 backend_instruction *inst; member in schedule_node
125 switch (inst->opcode) { in set_latency_gen4()
160 switch (inst->opcode) { in set_latency_gen7()
501 virtual int issue_time(backend_instruction *inst) = 0;
503 virtual void count_reads_remaining(backend_instruction *inst) = 0;
505 virtual void update_register_pressure(backend_instruction *inst) = 0;
506 virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
573 bool is_compressed(fs_inst *inst);
575 int issue_time(backend_instruction *inst);
[all …]
Dbrw_fs_copy_propagation.cpp158 foreach_inst_in_block(fs_inst, inst, block) { in setup_initial_values()
159 if (inst->dst.file != VGRF) in setup_initial_values()
164 if (regions_overlap(inst->dst, inst->size_written, in setup_initial_values()
166 regions_overlap(inst->dst, inst->size_written, in setup_initial_values()
283 can_take_stride(fs_inst *inst, unsigned arg, unsigned stride, in can_take_stride() argument
299 if (inst->is_3src(devinfo)) { in can_take_stride()
300 if (type_sz(inst->src[arg].type) > 4) in can_take_stride()
323 if (inst->is_math()) { in can_take_stride()
325 assert(inst->dst.stride == 1); in can_take_stride()
328 return stride == inst->dst.stride || stride == 0; in can_take_stride()
[all …]
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_transform.h49 struct tgsi_full_instruction *inst);
79 const struct tgsi_full_instruction *inst);
259 struct tgsi_full_instruction inst; in tgsi_transform_op1_inst() local
261 inst = tgsi_default_full_instruction(); in tgsi_transform_op1_inst()
262 inst.Instruction.Opcode = opcode; in tgsi_transform_op1_inst()
263 inst.Instruction.NumDstRegs = 1; in tgsi_transform_op1_inst()
264 inst.Dst[0].Register.File = dst_file, in tgsi_transform_op1_inst()
265 inst.Dst[0].Register.Index = dst_index; in tgsi_transform_op1_inst()
266 inst.Dst[0].Register.WriteMask = dst_writemask; in tgsi_transform_op1_inst()
267 inst.Instruction.NumSrcRegs = 1; in tgsi_transform_op1_inst()
[all …]
/external/pcre/dist2/src/sljit/
DsljitNativeX86_64.c31 sljit_u8 *inst; in emit_load_imm64() local
33 inst = (sljit_u8*)ensure_buf(compiler, 1 + 2 + sizeof(sljit_sw)); in emit_load_imm64()
34 FAIL_IF(!inst); in emit_load_imm64()
36 *inst++ = REX_W | ((reg_map[reg] <= 7) ? 0 : REX_B); in emit_load_imm64()
37 *inst++ = MOV_r_i32 + (reg_map[reg] & 0x7); in emit_load_imm64()
38 sljit_unaligned_store_sw(inst, imm); in emit_load_imm64()
95 sljit_u8 *inst; in sljit_emit_enter() local
109 inst = (sljit_u8*)ensure_buf(compiler, 1 + size); in sljit_emit_enter()
110 FAIL_IF(!inst); in sljit_emit_enter()
113 *inst++ = REX_B; in sljit_emit_enter()
[all …]
DsljitNativeX86_common.c259 #define INC_SIZE(s) (*inst++ = (s), compiler->size += (s))
261 #define PUSH_REG(r) (*inst++ = (PUSH_r + (r)))
262 #define POP_REG(r) (*inst++ = (POP_r + (r)))
263 #define RET() (*inst++ = (RET_near))
264 #define RET_I16(n) (*inst++ = (RET_i16), *inst++ = n, *inst++ = 0)
266 #define MOV_RM(mod, reg, rm) (*inst++ = (MOV_r_rm), *inst++ = (mod) << 6 | (reg) << 3 | (rm))
609 sljit_u8 *inst; in emit_save_flags() local
612 inst = (sljit_u8*)ensure_buf(compiler, 1 + 5); in emit_save_flags()
613 FAIL_IF(!inst); in emit_save_flags()
616 inst = (sljit_u8*)ensure_buf(compiler, 1 + 6); in emit_save_flags()
[all …]
/external/webrtc/webrtc/modules/audio_coding/codecs/cng/
Dwebrtc_cng.c148 WebRtcCngEncoder* inst = (WebRtcCngEncoder*) cng_inst; in WebRtcCng_InitEnc() local
149 memset(inst, 0, sizeof(WebRtcCngEncoder)); in WebRtcCng_InitEnc()
153 inst->errorcode = CNG_DISALLOWED_LPC_ORDER; in WebRtcCng_InitEnc()
157 inst->enc_sampfreq = fs; in WebRtcCng_InitEnc()
158 inst->enc_interval = interval; in WebRtcCng_InitEnc()
159 inst->enc_nrOfCoefs = quality; in WebRtcCng_InitEnc()
160 inst->enc_msSinceSID = 0; in WebRtcCng_InitEnc()
161 inst->enc_seed = 7777; /* For debugging only. */ in WebRtcCng_InitEnc()
162 inst->enc_Energy = 0; in WebRtcCng_InitEnc()
164 inst->enc_reflCoefs[i] = 0; in WebRtcCng_InitEnc()
[all …]
/external/mesa3d/src/mesa/program/
Dprogramopt.c254 struct prog_instruction *newInst, *inst; in _mesa_append_fog_code() local
296 inst = newInst; in _mesa_append_fog_code()
298 if (inst->Opcode == OPCODE_END) in _mesa_append_fog_code()
300 if (inst->DstReg.File == PROGRAM_OUTPUT && in _mesa_append_fog_code()
301 inst->DstReg.Index == FRAG_RESULT_COLOR) { in _mesa_append_fog_code()
303 inst->DstReg.File = PROGRAM_TEMPORARY; in _mesa_append_fog_code()
304 inst->DstReg.Index = colorTemp; in _mesa_append_fog_code()
305 inst->Saturate = saturate; in _mesa_append_fog_code()
308 inst++; in _mesa_append_fog_code()
310 assert(inst->Opcode == OPCODE_END); /* we'll overwrite this inst */ in _mesa_append_fog_code()
[all …]
/external/webrtc/webrtc/modules/audio_coding/codecs/opus/
Dopus_interface.c44 int16_t WebRtcOpus_EncoderCreate(OpusEncInst** inst, in WebRtcOpus_EncoderCreate() argument
48 if (!inst) in WebRtcOpus_EncoderCreate()
80 *inst = state; in WebRtcOpus_EncoderCreate()
84 int16_t WebRtcOpus_EncoderFree(OpusEncInst* inst) { in WebRtcOpus_EncoderFree() argument
85 if (inst) { in WebRtcOpus_EncoderFree()
86 opus_encoder_destroy(inst->encoder); in WebRtcOpus_EncoderFree()
87 free(inst->zero_counts); in WebRtcOpus_EncoderFree()
88 free(inst); in WebRtcOpus_EncoderFree()
95 int WebRtcOpus_Encode(OpusEncInst* inst, in WebRtcOpus_Encode() argument
110 const size_t channels = inst->channels; in WebRtcOpus_Encode()
[all …]
/external/webrtc/webrtc/modules/audio_coding/codecs/isac/main/source/
Disac_float_type.h21 static inline int16_t Control(instance_type* inst, in Control()
24 return WebRtcIsac_Control(inst, rate, framesize); in Control()
26 static inline int16_t ControlBwe(instance_type* inst, in ControlBwe()
30 return WebRtcIsac_ControlBwe(inst, rate_bps, frame_size_ms, in ControlBwe()
33 static inline int16_t Create(instance_type** inst) { in Create()
34 return WebRtcIsac_Create(inst); in Create()
36 static inline int DecodeInternal(instance_type* inst, in DecodeInternal()
41 return WebRtcIsac_Decode(inst, encoded, len, decoded, speech_type); in DecodeInternal()
43 static inline size_t DecodePlc(instance_type* inst, in DecodePlc()
46 return WebRtcIsac_DecodePlc(inst, decoded, num_lost_frames); in DecodePlc()
[all …]
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_asm.c36 check_uniforms(const struct etna_inst *inst) in check_uniforms() argument
43 const struct etna_inst_src *src = &inst->src[i]; in check_uniforms()
62 etna_assemble(uint32_t *out, const struct etna_inst *inst) in etna_assemble() argument
65 if (inst->imm && inst->src[2].use) in etna_assemble()
68 if (!check_uniforms(inst)) in etna_assemble()
71 out[0] = VIV_ISA_WORD_0_OPCODE(inst->opcode) | in etna_assemble()
72 VIV_ISA_WORD_0_COND(inst->cond) | in etna_assemble()
73 COND(inst->sat, VIV_ISA_WORD_0_SAT) | in etna_assemble()
74 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) | in etna_assemble()
75 VIV_ISA_WORD_0_DST_AMODE(inst->dst.amode) | in etna_assemble()
[all …]

12345678910>>...28