Home
last modified time | relevance | path

Searched refs:kSRegSize (Results 1 – 15 of 15) sorted by relevance

/external/vixl/src/aarch64/
Dlogic-aarch64.cc3955 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { \
3997 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in frecps()
4027 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in frsqrts()
4082 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmp()
4097 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fcmp_zero()
4115 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fabscmp()
4150 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fmla()
4181 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fmls()
4208 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fneg()
4237 if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { in fabs_()
[all …]
Doperands-aarch64.h151 (size_ == kSRegSize) || (size_ == kDRegSize) || in IsValidVRegister()
397 bool IsLaneSizeS() const { return GetLaneSizeInBits() == kSRegSize; } in IsLaneSizeS()
456 const VRegister s##N(N, kSRegSize); \
Dinstructions-aarch64.h67 const unsigned kSRegSize = 32; variable
69 const unsigned kSRegSizeInBytes = kSRegSize / 8;
Dinstructions-aarch64.cc548 return kSRegSize; in RegisterSizeInBitsFromFormat()
Dmacro-assembler-aarch64.h857 PushSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PushSRegList()
860 PopSizeRegList(regs, kSRegSize, CPURegister::kVRegister); in PopSRegList()
927 PeekSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PeekSRegList()
930 PokeSizeRegList(regs, offset, kSRegSize, CPURegister::kVRegister); in PokeSRegList()
Ddisasm-aarch64.cc4035 case kSRegSize: in AppendRegisterNameToOutput()
4317 reg_size = kSRegSize; in SubstituteRegisterField()
Dassembler-aarch64.cc4637 case kSRegSize: in LoadOpFor()
4660 case kSRegSize: in StoreOpFor()
Dsimulator-aarch64.h1216 case kSRegSize:
/external/vixl/examples/aarch64/
Dneon-matrix-multiply.cc49 VRegister v_in = VRegister(in_column, kSRegSize); in GenerateMultiplyColumn()
/external/v8/src/arm64/
Dsimulator-arm64.h453 if (sizeof(value) <= kSRegSize) {
480 DCHECK((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
541 kPrintSRegValue = 1 << kSRegSize,
Dsimulator-arm64.cc1228 case kSRegSize: in PrintReadFP()
1292 case kSRegSize: in PrintWriteFP()
1764 DCHECK(access_size == kSRegSize); in LoadStorePairHelper()
1794 DCHECK(access_size == kSRegSize); in LoadStorePairHelper()
1869 LogReadFP(address, kSRegSize, rt); in VisitLoadLiteral()
Dconstants-arm64.h55 const int kSRegSize = kSRegSizeInBits >> 3; variable
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc203 VIXL_ASSERT((d_size == kDRegSize) || (d_size == kSRegSize)); in Test1Op_Helper()
204 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize)); in Test1Op_Helper()
323 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in Test2Op_Helper()
456 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in Test3Op_Helper()
605 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmp_Helper()
744 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); in TestCmpZero_Helper()
872 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize)); in TestFPToFixed_Helper()
924 VIXL_ASSERT((n_size == kDRegSize) || (n_size == kSRegSize)); in TestFPToInt_Helper()
1526 bool destructive = (vd_bits == kBRegSize) || (vd_bits == kSRegSize); in Test1OpAcrossNEON_Helper()
Dtest-utils-aarch64.cc322 s[i] = FPRegister(n, kSRegSize); in PopulateFPRegisterArray()
Dtest-assembler-aarch64.cc13900 ASSERT_EQUAL_FP64(RawbitsToDouble((base_d >> kSRegSize) | in TEST()
13901 ((2 * base_d) << kSRegSize)), in TEST()
13905 ASSERT_EQUAL_FP32(RawbitsToFloat((4 * base_d) >> kSRegSize), s17); in TEST()
13999 VIXL_CHECK(array[12] == ((1 * low_base) << kSRegSize)); in TEST()
14000 VIXL_CHECK(array[13] == (((2 * low_base) << kSRegSize) | (1 * high_base))); in TEST()
14001 VIXL_CHECK(array[14] == (((3 * low_base) << kSRegSize) | (2 * high_base))); in TEST()
14002 VIXL_CHECK(array[15] == (((4 * low_base) << kSRegSize) | (3 * high_base))); in TEST()
14003 VIXL_CHECK(array[16] == (((1 * low_base) << kSRegSize) | (4 * high_base))); in TEST()
14004 VIXL_CHECK(array[17] == (((2 * low_base) << kSRegSize) | (1 * high_base))); in TEST()
14005 VIXL_CHECK(array[18] == (((3 * low_base) << kSRegSize) | (2 * high_base))); in TEST()
[all …]