/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | intrinsics.ll | 12 ; CHECK: mcr2 13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind 33 declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
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/external/llvm/test/CodeGen/ARM/ |
D | intrinsics-coprocessor.ll | 12 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4 13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind 69 declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
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/external/llvm/test/MC/Disassembler/ARM/ |
D | invalid-thumbv8.txt | 44 # CHECK-V7: mcr2 49 # CHECK-V7: mcr2 54 # CHECK-V7: mcr2
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D | invalid-armv8.txt | 44 # CHECK-V7: mcr2 49 # CHECK-V7: mcr2 54 # CHECK-V7: mcr2
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D | arm-tests.txt | 99 # CHECK: mcr2 p0, #0, r2, c1, c0, #7
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D | thumb2.txt | 1023 # CHECK: mcr2 p7, #1, r5, c1, c1, #4
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D | basic-arm-instructions.txt | 712 # CHECK: mcr2 p7, #1, r5, c1, c1, #4
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/external/clang/test/CodeGen/ |
D | builtins-arm.c | 179 void mcr2(unsigned a) { in mcr2() function
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | diagnostics.s | 81 mcr2 p7, #8, r5, c1, c1, #4 82 mcr2 p7, #1, r5, c1, c1, #8
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D | basic-arm-instructions.s | 793 mcr2 p7, #1, r5, c1, c1, #4 796 @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
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D | basic-thumb2-instructions.s | 1068 mcr2 p7, #1, r5, c1, c1, #4 1071 @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57]
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | arm-tests.txt | 75 # CHECK: mcr2 p0, #0, r2, c1, c0, #7
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D | basic-arm-instructions.txt | 631 # CHECK: mcr2 p7, #1, r5, c1, c1, #4
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D | thumb2.txt | 906 # CHECK: mcr2 p7, #1, r5, c1, c1, #4
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/external/llvm/test/MC/ARM/ |
D | diagnostics.s | 143 mcr2 p7, #8, r5, c1, c1, #4 144 mcr2 p7, #1, r5, c1, c1, #8
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D | basic-thumb2-instructions.s | 1377 mcr2 p7, #1, r5, c1, c1, #4 1379 mcr2 p4, #2, r2, c1, c3 1382 @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] 1384 @ CHECK: mcr2 p4, #2, r2, c1, c3, #0 @ encoding: [0x41,0xfe,0x13,0x24]
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D | basic-arm-instructions.s | 1244 mcr2 p7, #1, r5, c1, c1, #4 1247 @ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
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/external/capstone/suite/MC/ARM/ |
D | basic-thumb2-instructions.s.cs | 428 0x21,0xfe,0x91,0x57 = mcr2 p7, #1, r5, c1, c1, #4 430 0x41,0xfe,0x13,0x24 = mcr2 p4, #2, r2, c1, c3, #0
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D | basic-arm-instructions.s.cs | 343 0x91,0x57,0x21,0xfe = mcr2 p7, #1, r5, c1, c1, #4
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/external/v8/src/arm/ |
D | assembler-arm.h | 1069 void mcr2(Coprocessor coproc, int opcode_1,
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D | assembler-arm.cc | 2341 void Assembler::mcr2(Coprocessor coproc, int opcode_1, Register rd, in mcr2() function in v8::internal::Assembler
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 4203 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 4210 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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D | ARMInstrInfo.td | 5093 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5100 def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm",
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/external/capstone/arch/ARM/ |
D | ARMGenAsmWriter.inc | 8890 AsmString = "mcr2 $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06"; 10918 AsmString = "mcr2$\xFF\x07\x01} $\xFF\x01\x05, $\x02, $\x03, $\xFF\x04\x06, $\xFF\x05\x06";
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 3670 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
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