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Searched refs:mrc2 (Results 1 – 25 of 30) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dintrinsics.ll10 ; CHECK: mrc2
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
35 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dthumb2-diagnostics.s35 mrc2 p14, #8, r1, c1, c2, #4
36 mrc2 p14, #0, r1, c1, c2, #9
Ddiagnostics.s110 mrc2 p14, #8, r1, c1, c2, #4
111 mrc2 p14, #0, r1, c1, c2, #9
Dbasic-arm-instructions.s880 mrc2 p14, #0, r1, c1, c2, #4
883 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
Dbasic-thumb2-instructions.s1145 mrc2 p14, #0, r1, c1, c2, #4
1148 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
/external/llvm/test/CodeGen/ARM/
Dintrinsics-coprocessor.ll10 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
71 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv8.txt64 # CHECK-V7: mrc2
69 # CHECK-V7: mrc2
74 # CHECK-V7: mrc2
Dinvalid-armv8.txt64 # CHECK-V7: mrc2
69 # CHECK-V7: mrc2
74 # CHECK-V7: mrc2
Dbasic-arm-instructions.txt816 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
817 # CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1
Dthumb2.txt1089 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
/external/clang/test/CodeGen/
Dbuiltins-arm.c166 unsigned mrc2() { in mrc2() function
/external/llvm/test/MC/ARM/
Dthumb2-diagnostics.s38 mrc2 p14, #8, r1, c1, c2, #4
39 mrc2 p14, #0, r1, c1, c2, #9
Ddiagnostics.s178 mrc2 p14, #8, r1, c1, c2, #4
179 mrc2 p14, #0, r1, c1, c2, #9
Dbasic-thumb2-instructions.s1523 mrc2 p12, #3, r3, c3, c4
1524 mrc2 p14, #0, r1, c1, c2, #4
1525 mrc2 p8, #7, apsr_nzcv, c15, c0, #1
1530 @ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
1531 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
1532 @ CHECK: mrc2 p8, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xf8]
Dbasic-arm-instructions.s1384 mrc2 p14, #0, r1, c1, c2, #4
1385 mrc2 p9, #7, apsr_nzcv, c15, c0, #1
1389 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
1390 @ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
/external/capstone/suite/MC/ARM/
Dbasic-thumb2-instructions.s.cs483 0x73,0xfe,0x14,0x3c = mrc2 p12, #3, r3, c3, c4, #0
484 0x11,0xfe,0x92,0x1e = mrc2 p14, #0, r1, c1, c2, #4
485 0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1
Dbasic-arm-instructions.s.cs379 0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4
380 0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1
/external/v8/src/arm/
Dassembler-arm.h1077 void mrc2(Coprocessor coproc, int opcode_1,
Dassembler-arm.cc2359 void Assembler::mrc2(Coprocessor coproc, int opcode_1, Register rd, in mrc2() function in v8::internal::Assembler
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt718 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
Dthumb2.txt972 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4222 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
4227 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
DARMInstrInfo.td5103 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
5108 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc8945 AsmString = "mrc2 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06";
10949 AsmString = "mrc2$\xFF\x07\x01} $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06";
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td3681 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,

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