/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
D | intrinsics.ll | 10 ; CHECK: mrc2 11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind 35 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | thumb2-diagnostics.s | 35 mrc2 p14, #8, r1, c1, c2, #4 36 mrc2 p14, #0, r1, c1, c2, #9
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D | diagnostics.s | 110 mrc2 p14, #8, r1, c1, c2, #4 111 mrc2 p14, #0, r1, c1, c2, #9
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D | basic-arm-instructions.s | 880 mrc2 p14, #0, r1, c1, c2, #4 883 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
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D | basic-thumb2-instructions.s | 1145 mrc2 p14, #0, r1, c1, c2, #4 1148 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
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/external/llvm/test/CodeGen/ARM/ |
D | intrinsics-coprocessor.ll | 10 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4 11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind 71 declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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/external/llvm/test/MC/Disassembler/ARM/ |
D | invalid-thumbv8.txt | 64 # CHECK-V7: mrc2 69 # CHECK-V7: mrc2 74 # CHECK-V7: mrc2
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D | invalid-armv8.txt | 64 # CHECK-V7: mrc2 69 # CHECK-V7: mrc2 74 # CHECK-V7: mrc2
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D | basic-arm-instructions.txt | 816 # CHECK: mrc2 p14, #0, r1, c1, c2, #4 817 # CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1
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D | thumb2.txt | 1089 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
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/external/clang/test/CodeGen/ |
D | builtins-arm.c | 166 unsigned mrc2() { in mrc2() function
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/external/llvm/test/MC/ARM/ |
D | thumb2-diagnostics.s | 38 mrc2 p14, #8, r1, c1, c2, #4 39 mrc2 p14, #0, r1, c1, c2, #9
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D | diagnostics.s | 178 mrc2 p14, #8, r1, c1, c2, #4 179 mrc2 p14, #0, r1, c1, c2, #9
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D | basic-thumb2-instructions.s | 1523 mrc2 p12, #3, r3, c3, c4 1524 mrc2 p14, #0, r1, c1, c2, #4 1525 mrc2 p8, #7, apsr_nzcv, c15, c0, #1 1530 @ CHECK: mrc2 p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c] 1531 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e] 1532 @ CHECK: mrc2 p8, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0xff,0xfe,0x30,0xf8]
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D | basic-arm-instructions.s | 1384 mrc2 p14, #0, r1, c1, c2, #4 1385 mrc2 p9, #7, apsr_nzcv, c15, c0, #1 1389 @ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] 1390 @ CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xf9,0xff,0xfe]
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/external/capstone/suite/MC/ARM/ |
D | basic-thumb2-instructions.s.cs | 483 0x73,0xfe,0x14,0x3c = mrc2 p12, #3, r3, c3, c4, #0 484 0x11,0xfe,0x92,0x1e = mrc2 p14, #0, r1, c1, c2, #4 485 0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1
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D | basic-arm-instructions.s.cs | 379 0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4 380 0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1
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/external/v8/src/arm/ |
D | assembler-arm.h | 1077 void mrc2(Coprocessor coproc, int opcode_1,
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D | assembler-arm.cc | 2359 void Assembler::mrc2(Coprocessor coproc, int opcode_1, Register rd, in mrc2() function in v8::internal::Assembler
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | basic-arm-instructions.txt | 718 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
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D | thumb2.txt | 972 # CHECK: mrc2 p14, #0, r1, c1, c2, #4
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 4222 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 4227 def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm",
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D | ARMInstrInfo.td | 5103 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5108 def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm",
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/external/capstone/arch/ARM/ |
D | ARMGenAsmWriter.inc | 8945 AsmString = "mrc2 $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06"; 10949 AsmString = "mrc2$\xFF\x07\x01} $\xFF\x02\x05, $\x03, $\x01, $\xFF\x04\x06, $\xFF\x05\x06";
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 3681 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
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