| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
59 DOTP_CONST_PAIR(reg2, reg6, cospi_24_64, cospi_8_64, reg2, reg6); in idct32x8_row_even_process_store()
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1); in idct32x8_row_even_process_store()
73 reg4 = reg6 + reg2; in idct32x8_row_even_process_store()
74 reg6 = reg6 - reg2; in idct32x8_row_even_process_store()
88 DOTP_CONST_PAIR((-reg6), reg1, cospi_24_64, cospi_8_64, reg6, reg1); in idct32x8_row_even_process_store()
90 vec0 = reg0 - reg6; in idct32x8_row_even_process_store()
[all …]
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| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
24 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
28 DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6); in vpx_idct16_1d_rows_msa()
29 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
36 ADD4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg2, reg14, reg6, in vpx_idct16_1d_rows_msa()
70 reg2 = reg6 + loc0; in vpx_idct16_1d_rows_msa()
[all …]
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| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
142 res8 = (v16u8)__msa_ilvr_w((v4i32)reg6, (v4i32)reg2); in TransposeWx16_MSA()
143 res9 = (v16u8)__msa_ilvl_w((v4i32)reg6, (v4i32)reg2); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
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| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
898 reg6 = reg0 * const_0x70; in ARGBToUVRow_MSA()
902 reg6 += const_0x8080; in ARGBToUVRow_MSA()
916 reg6 -= reg8; in ARGBToUVRow_MSA()
920 reg6 = (v8u16)__msa_srai_h((v8i16)reg6, 8); in ARGBToUVRow_MSA()
924 dst0 = (v16u8)__msa_pckev_b((v16i8)reg7, (v16i8)reg6); in ARGBToUVRow_MSA()
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ARGBAttenuateRow_MSA() local
1266 reg6 = (v4u32)__msa_ilvr_h(zero, (v8i16)vec7); in ARGBAttenuateRow_MSA()
1274 reg6 *= (v4u32)__msa_ilvr_h(zero, (v8i16)vec3); in ARGBAttenuateRow_MSA()
1282 reg6 = (v4u32)__msa_srai_w((v4i32)reg6, 24); in ARGBAttenuateRow_MSA()
[all …]
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| D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
163 reg6 = (v8u16)__msa_pckod_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
165 reg4 += reg6; in ScaleARGBRowDownEvenBox_MSA()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 6 …eg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg …
28 %20 = extractelement <4 x float> %reg6, i32 0
29 %21 = extractelement <4 x float> %reg6, i32 1
30 %22 = extractelement <4 x float> %reg6, i32 2
31 %23 = extractelement <4 x float> %reg6, i32 3
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| D | big_alu.ll | 5 …eg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg …
45 %tmp38 = extractelement <4 x float> %reg6, i32 0
46 %tmp39 = extractelement <4 x float> %reg6, i32 1
47 %tmp40 = extractelement <4 x float> %reg6, i32 2
48 %tmp41 = extractelement <4 x float> %reg6, i32 3
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| /external/elfutils/tests/ |
| D | run-varlocs.sh | 64 [40051c,40052b) {reg6}
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| D | run-addrcfi.sh | 39 integer reg6 (%esi): same_value
86 integer reg6 (%esi): same_value
138 integer reg6 (%rbp): same_value
204 integer reg6 (%rbp): same_value
308 integer reg6 (r6): undefined
1330 integer reg6 (r6): undefined
2358 integer reg6 (r6): undefined
3384 integer reg6 (%r6): same_value
3461 integer reg6 (%r6): same_value
3539 integer reg6 (r6): same_value
[all …]
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| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 58 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], [pc, r[[reg5]]]
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 479 const CPURegister& reg6 = NoReg,
493 const CPURegister& reg6 = NoCPUReg,
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| /external/v8/src/arm/ |
| D | macro-assembler-arm.cc | 3714 Register reg6) { in GetRegisterThatIsNotOneOf() argument
3721 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
3740 Register reg6, in AreAliased() argument
3744 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
3753 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
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| D | macro-assembler-arm.h | 69 Register reg6 = no_reg);
78 Register reg6 = no_reg,
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 229 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
266 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
274 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| D | assembler-arm64.h | 360 const CPURegister& reg6 = NoReg,
373 const CPURegister& reg6 = NoCPUReg,
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| /external/v8/src/ppc/ |
| D | macro-assembler-ppc.cc | 4239 Register reg6) { in GetRegisterThatIsNotOneOf() argument
4246 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
4261 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
4264 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
4274 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
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| D | macro-assembler-ppc.h | 63 Register reg6 = no_reg);
69 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/llvm/include/llvm/Support/ |
| D | Dwarf.def | 207 HANDLE_DW_OP(0x56, reg6)
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| /external/v8/src/x87/ |
| D | macro-assembler-x87.cc | 2496 Register reg6, in AreAliased() argument
2500 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
2509 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
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| /external/v8/src/ia32/ |
| D | macro-assembler-ia32.cc | 2650 Register reg6, in AreAliased() argument
2654 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
2663 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
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| /external/v8/src/s390/ |
| D | macro-assembler-s390.cc | 3185 Register reg6) { in GetRegisterThatIsNotOneOf() argument
3192 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
5260 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
5263 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
5273 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
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| D | macro-assembler-s390.h | 70 Register reg6 = no_reg);
75 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/v8/src/mips/ |
| D | macro-assembler-mips.cc | 6379 Register reg6) { in GetRegisterThatIsNotOneOf() argument
6386 if (reg6.is_valid()) regs |= reg6.bit(); in GetRegisterThatIsNotOneOf()
6400 Register reg5, Register reg6, Register reg7, Register reg8, in AreAliased() argument
6403 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + in AreAliased()
6413 if (reg6.is_valid()) regs |= reg6.bit(); in AreAliased()
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| D | macro-assembler-mips.h | 101 Register reg6 = no_reg);
105 Register reg6 = no_reg, Register reg7 = no_reg,
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| /external/elfutils/libdw/ |
| D | known-dwarf.h | 526 DWARF_ONE_KNOWN_DW_OP (reg6, DW_OP_reg6) \
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