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Searched refs:v32i16 (Results 1 – 22 of 22) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h83 v32i16 = 35, // 32 x i16 enumerator
266 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
339 case v32i16: in getVectorElementType()
386 case v32i16: in getVectorNumElements()
498 case v32i16: in getSizeInBits()
619 if (NumElements == 32) return MVT::v32i16; in getVectorVT()
DValueTypes.td60 def v32i16 : ValueType<512, 35>; // 32 x i16 vector value
/external/llvm/lib/Target/X86/
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
671 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
677 v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
DX86InstrAVX512.td380 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
403 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
[all …]
DX86ISelLowering.cpp1144 setLoadExtAction(ExtType, MVT::v32i16, MVT::v32i8, Legal); in X86TargetLowering()
1162 MVT::v8i64, MVT::v32i16, MVT::v64i8}) { in X86TargetLowering()
1407 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) { in X86TargetLowering()
1413 addRegisterClass(MVT::v32i16, &X86::VR512RegClass); in X86TargetLowering()
1428 setOperationAction(ISD::MUL, MVT::v32i16, Legal); in X86TargetLowering()
1430 setOperationAction(ISD::MULHS, MVT::v32i16, Legal); in X86TargetLowering()
1431 setOperationAction(ISD::MULHU, MVT::v32i16, Legal); in X86TargetLowering()
1434 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom); in X86TargetLowering()
1438 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom); in X86TargetLowering()
1440 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom); in X86TargetLowering()
[all …]
DX86RegisterInfo.td496 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86FastISel.cpp475 case MVT::v32i16: in X86FastEmitLoad()
620 case MVT::v32i16: in X86FastEmitStore()
DX86InstrFragmentsSIMD.td625 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
/external/llvm/lib/IR/
DValueTypes.cpp167 case MVT::v32i16: return "v32i16"; in getEVTString()
245 case MVT::v32i16: return VectorType::get(Type::getInt16Ty(Context), 32); in getTypeForEVT()
/external/llvm/test/CodeGen/X86/
Dvector-popcnt-512.ll138 %out = call <32 x i16> @llvm.ctpop.v32i16(<32 x i16> %in)
178 declare <32 x i16> @llvm.ctpop.v32i16(<32 x i16>)
Dvector-lzcnt-512.ll69 %out = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %in, i1 0)
101 %out = call <32 x i16> @llvm.ctlz.v32i16(<32 x i16> %in, i1 -1)
219 declare <32 x i16> @llvm.ctlz.v32i16(<32 x i16>, i1)
Dvector-tzcnt-512.ll309 %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 0)
383 %out = call <32 x i16> @llvm.cttz.v32i16(<32 x i16> %in, i1 -1)
513 declare <32 x i16> @llvm.cttz.v32i16(<32 x i16>, i1)
Dvector-bitreverse.ll2792 %b = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %a)
3770 declare <32 x i16> @llvm.bitreverse.v32i16(<32 x i16>) readnone
Dmasked_memop.ll6917 …%res = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* %addr, i32 4, <32 x i1>%mask,…
6920 declare <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>*, i32, <32 x i1>, <32 x i16>)
10402 …call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> %val, <32 x i16>* %addr, i32 4, <32 x i1>%…
10406 declare void @llvm.masked.store.v32i16.p0v32i16(<32 x i16>, <32 x i16>*, i32, <32 x i1>)
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
412 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || in RetCC_Hexagon()
543 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
902 VT == MVT::v32i16 || VT == MVT::v64i8); in getIndexedAddressParts()
1119 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1756 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2873 case MVT::v32i16: in getRegForInlineAsmConstraint()
2884 case MVT::v32i16: in getRegForInlineAsmConstraint()
3031 case MVT::v32i16: in allowsMisalignedMemoryAccesses()
[all …]
DHexagonIntrinsicsV60.td89 def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
90 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
109 def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
110 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
DHexagonRegisterInfo.td226 def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
DHexagonISelDAGToDAG.cpp276 case MVT::v32i16: in SelectIndexedLoad()
564 case MVT::v32i16: in SelectIndexedStore()
DHexagonInstrInfoV60.td849 defm : vS32b_ai_pats <v32i16, v64i16>;
914 defm : vL32b_ai_pats <v32i16, v64i16>;
DHexagonInstrInfo.cpp2626 VT == MVT::v32i16 || VT == MVT::v64i8) { in isValidAutoIncImm()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp95 case MVT::v32i16: return "MVT::v32i16"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td193 def llvm_v32i16_ty : LLVMType<v32i16>; // 32 x i16