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Searched refs:v64i8 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h74 v64i8 = 27, // 64 x i8 enumerator
265 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
331 case v64i8: in getVectorElementType()
381 case v64i8: in getVectorNumElements()
497 case v64i8: in getSizeInBits()
609 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
DValueTypes.td51 def v64i8 : ValueType<512, 27>; // 64 x i8 vector value
/external/llvm/lib/Target/X86/
DX86CallingConv.td51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
328 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
601 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
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DX86InstrAVX512.td381 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
386 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
396 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
407 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
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DX86ISelLowering.cpp1162 MVT::v8i64, MVT::v32i16, MVT::v64i8}) { in X86TargetLowering()
1407 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) { in X86TargetLowering()
1414 addRegisterClass(MVT::v64i8, &X86::VR512RegClass); in X86TargetLowering()
1429 setOperationAction(ISD::MUL, MVT::v64i8, Custom); in X86TargetLowering()
1435 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom); in X86TargetLowering()
1439 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom); in X86TargetLowering()
1441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom); in X86TargetLowering()
1443 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v64i8, Custom); in X86TargetLowering()
1452 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom); in X86TargetLowering()
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
DX86RegisterInfo.td496 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86FastISel.cpp476 case MVT::v64i8: in X86FastEmitLoad()
621 case MVT::v64i8: in X86FastEmitStore()
DX86InstrFragmentsSIMD.td624 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
/external/llvm/lib/IR/
DValueTypes.cpp159 case MVT::v64i8: return "v64i8"; in getEVTString()
237 case MVT::v64i8: return VectorType::get(Type::getInt8Ty(Context), 64); in getTypeForEVT()
/external/llvm/test/CodeGen/X86/
Dvector-popcnt-512.ll172 %out = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %in)
179 declare <64 x i8> @llvm.ctpop.v64i8(<64 x i8>)
Dvector-lzcnt-512.ll157 %out = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %in, i1 0)
213 %out = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %in, i1 -1)
220 declare <64 x i8> @llvm.ctlz.v64i8(<64 x i8>, i1)
Dvector-tzcnt-512.ll445 %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 0)
507 %out = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %in, i1 -1)
514 declare <64 x i8> @llvm.cttz.v64i8(<64 x i8>, i1)
Dvector-bitreverse.ll2442 %b = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %a)
3769 declare <64 x i8> @llvm.bitreverse.v64i8(<64 x i8>) readnone
Dmasked_memop.ll5543 …%res = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* %addr, i32 4, <64 x i1>%mask, <64…
5546 declare <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>*, i32, <64 x i1>, <64 x i8>)
9221 …call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> %val, <64 x i8>* %addr, i32 4, <64 x i1>%mask)
9224 declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp198 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) { in CC_Hexagon_VarArg()
338 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { in CC_HexagonVector()
412 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 || in RetCC_Hexagon()
544 ty == MVT::v64i8 || in IsHvxVectorType()
902 VT == MVT::v32i16 || VT == MVT::v64i8); in getIndexedAddressParts()
1119 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) { in LowerFormalArguments()
1755 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2875 case MVT::v64i8: in getRegForInlineAsmConstraint()
2885 case MVT::v64i8: in getRegForInlineAsmConstraint()
3028 case MVT::v64i8: in allowsMisalignedMemoryAccesses()
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DHexagonIntrinsicsV60.td94 def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
95 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
114 def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
115 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1),
DHexagonRegisterInfo.td226 def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512,
DHexagonISelDAGToDAG.cpp275 case MVT::v64i8: in SelectIndexedLoad()
563 case MVT::v64i8: in SelectIndexedStore()
DHexagonInstrInfoV60.td848 defm : vS32b_ai_pats <v64i8, v128i8>;
913 defm : vL32b_ai_pats <v64i8, v128i8>;
DHexagonInstrInfo.cpp2626 VT == MVT::v32i16 || VT == MVT::v64i8) { in isValidAutoIncImm()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp87 case MVT::v64i8: return "MVT::v64i8"; in getEnumName()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td306 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
/external/llvm/include/llvm/IR/
DIntrinsics.td184 def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8