/external/llvm/test/CodeGen/ARM/ |
D | vminmaxnm-safe.ll | 25 ; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} 28 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 34 ; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 37 %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 45 ; CHECK-NOT: vminnm.f32 53 ; CHECK-NOT: vminnm.f64 61 ; CHECK-NOT: vminnm.f32 69 ; CHECK-NOT: vminnm.f64 77 ; CHECK-NOT: vminnm.f32 85 ; CHECK-NOT: vminnm.f32 [all …]
|
D | vminmaxnm.ll | 8 ; CHECK: vminnm.f32 17 ; CHECK: vminnm.f64 26 ; CHECK: vminnm.f32 35 ; CHECK: vminnm.f64 44 ; CHECK: vminnm.f32 53 ; CHECK: vminnm.f32 62 ; CHECK: vminnm.f32 71 ; CHECK: vminnm.f64 153 ; CHECK: vminnm.f32 154 ; CHECK: vminnm.f32 [all …]
|
/external/llvm/test/MC/ARM/ |
D | neon-v8.s | 7 vminnm.f32 d5, d4, d30 8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3] 9 vminnm.f32 q0, q13, q2 10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
|
D | thumb-neon-v8.s | 7 vminnm.f32 d5, d4, d30 8 @ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f] 9 vminnm.f32 q0, q13, q2 10 @ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
|
D | fp-armv8.s | 87 vminnm.f32 s0, s0, s12 88 @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x46,0x0a,0x80,0xfe] 89 vminnm.f64 d4, d6, d9 90 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x49,0x4b,0x86,0xfe]
|
D | thumb-fp-armv8.s | 90 vminnm.f32 s0, s0, s12 91 @ CHECK: vminnm.f32 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x0a] 92 vminnm.f64 d4, d6, d9 93 @ CHECK: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
|
D | directive-arch_extension-simd.s | 21 vminnm.f32 s0, s0, s0 26 vminnm.f64 d0, d0, d0 129 vminnm.f32 s0, s0, s0 134 vminnm.f64 d0, d0, d0
|
D | fullfp16-neon.s | 207 vminnm.f16 d0, d1, d2 208 vminnm.f16 q0, q1, q2 209 @ ARM: vminnm.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x31,0xf3] 210 @ ARM: vminnm.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x32,0xf3] 211 @ THUMB: vminnm.f16 d0, d1, d2 @ encoding: [0x31,0xff,0x12,0x0f] 212 @ THUMB: vminnm.f16 q0, q1, q2 @ encoding: [0x32,0xff,0x54,0x0f]
|
D | directive-arch_extension-fp.s | 32 vminnm.f32 s0, s0, s0 45 vminnm.f64 d0, d0, d0 168 vminnm.f32 s0, s0, s0 181 vminnm.f64 d0, d0, d0
|
D | fullfp16.s | 165 vminnm.f16 s0, s0, s12 166 @ ARM: vminnm.f16 s0, s0, s12 @ encoding: [0x46,0x09,0x80,0xfe] 167 @ THUMB: vminnm.f16 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x09]
|
D | fullfp16-neon-neg.s | 151 vminnm.f16 d0, d1, d2 152 vminnm.f16 q0, q1, q2
|
D | invalid-fp-armv8.s | 48 vminnm.f64 s3, s2, s1
|
D | fullfp16-neg.s | 122 vminnm.f16 s0, s0, s12
|
/external/capstone/suite/MC/ARM/ |
D | neon-v8.s.cs | 4 0x3e,0x5f,0x24,0xf3 = vminnm.f32 d5, d4, d30 5 0xd4,0x0f,0x2a,0xf3 = vminnm.f32 q0, q13, q2
|
D | thumb-neon-v8.s.cs | 4 0x24,0xff,0x3e,0x5f = vminnm.f32 d5, d4, d30 5 0x2a,0xff,0xd4,0x0f = vminnm.f32 q0, q13, q2
|
D | fp-armv8.s.cs | 36 0x46,0x0a,0x80,0xfe = vminnm.f32 s0, s0, s12 37 0x49,0x4b,0x86,0xfe = vminnm.f64 d4, d6, d9
|
D | thumb-fp-armv8.s.cs | 36 0x80,0xfe,0x46,0x0a = vminnm.f32 s0, s0, s12 37 0x86,0xfe,0x49,0x4b = vminnm.f64 d4, d6, d9
|
/external/llvm/test/MC/Disassembler/ARM/ |
D | thumb-neon-v8.txt | 8 # CHECK: vminnm.f32 d5, d4, d30 10 # CHECK: vminnm.f32 q0, q13, q2
|
D | neon-v8.txt | 8 # CHECK: vminnm.f32 d5, d4, d30 10 # CHECK: vminnm.f32 q0, q13, q2
|
D | thumb-fp-armv8.txt | 113 # CHECK: vminnm.f32 s0, s0, s12 116 # CHECK: vminnm.f64 d4, d6, d9
|
D | fp-armv8.txt | 109 # CHECK: vminnm.f32 s0, s0, s12 112 # CHECK: vminnm.f64 d4, d6, d9
|
D | fullfp16-neon-arm.txt | 129 # CHECK: vminnm.f16 d0, d1, d2 130 # CHECK: vminnm.f16 q0, q1, q2
|
D | fullfp16-neon-thumb.txt | 129 # CHECK: vminnm.f16 d0, d1, d2 130 # CHECK: vminnm.f16 q0, q1, q2
|
D | fullfp16-thumb.txt | 121 # CHECK: vminnm.f16 s0, s0, s12
|
D | fullfp16-arm.txt | 121 # CHECK: vminnm.f16 s0, s0, s12
|