Home
last modified time | relevance | path

Searched refs:vs_inputs (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_draw_upload.c539 GLbitfield64 vs_inputs = vs_prog_data->inputs_read; in brw_prepare_vertices() local
559 vs_inputs |= VERT_BIT_EDGEFLAG; in brw_prepare_vertices()
567 while (vs_inputs) { in brw_prepare_vertices()
568 GLuint first = ffsll(vs_inputs) - 1; in brw_prepare_vertices()
575 vs_inputs &= ~BITFIELD64_BIT(first); in brw_prepare_vertices()
577 vs_inputs &= ~BITFIELD64_BIT(first + 1); in brw_prepare_vertices()
Dbrw_vec4.cpp1736 GLbitfield64 vs_inputs = vs_prog_data->inputs_read; in setup_attributes() local
1737 while (vs_inputs) { in setup_attributes()
1738 GLuint first = ffsll(vs_inputs) - 1; in setup_attributes()
1744 vs_inputs &= ~BITFIELD64_BIT(first + c); in setup_attributes()
/external/mesa3d/src/intel/blorp/
Dblorp_priv.h185 struct blorp_vs_inputs vs_inputs; member
Dblorp_genX_exec.h211 assert(sizeof(params->vs_inputs) == 16); in blorp_emit_input_varying_data()
212 memcpy(inputs, &params->vs_inputs, sizeof(params->vs_inputs)); in blorp_emit_input_varying_data()
Dblorp_clear.c654 params.vs_inputs.base_layer = start_layer; in blorp_clear_attachments()
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_ureg.c119 unsigned vs_inputs[PIPE_MAX_ATTRIBS/32]; member
347 assert(index / 32 < ARRAY_SIZE(ureg->vs_inputs)); in ureg_DECL_vs_input()
349 ureg->vs_inputs[index/32] |= 1 << (index % 32); in ureg_DECL_vs_input()
1850 if (ureg->vs_inputs[i/32] & (1u << (i%32))) { in emit_decls()