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/external/llvm/test/MC/ARM/
Dneon-table-encoding.s3 vtbl.8 d16, {d17}, d16
4 vtbl.8 d16, {d16, d17}, d18
5 vtbl.8 d16, {d16, d17, d18}, d20
6 vtbl.8 d16, {d16, d17, d18, d19}, d20
8 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
9 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
10 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
11 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
Dneont2-table-encoding.s5 vtbl.8 d16, {d17}, d16
6 vtbl.8 d16, {d16, d17}, d18
7 vtbl.8 d16, {d16, d17, d18}, d20
8 vtbl.8 d16, {d16, d17, d18, d19}, d20
10 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xf1,0xff,0xa0,0x08]
11 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xa2,0x09]
12 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xf0,0xff,0xa4,0x0a]
13 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xf0,0xff,0xa4,0x0b]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-table-encoding.s4 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3]
5 vtbl.8 d16, {d17}, d16
6 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3]
7 vtbl.8 d16, {d16, d17}, d18
8 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3]
9 vtbl.8 d16, {d16, d17, d18}, d20
10 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
11 vtbl.8 d16, {d16, d17, d18, d19}, d20
Dneont2-table-encoding.s6 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xff]
7 vtbl.8 d16, {d17}, d16
8 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xff]
9 vtbl.8 d16, {d16, d17}, d18
10 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xff]
11 vtbl.8 d16, {d16, d17, d18}, d20
12 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xff]
13 vtbl.8 d16, {d16, d17, d18, d19}, d20
/external/mesa3d/src/gallium/auxiliary/pipebuffer/
Dpb_buffer.h111 const struct pb_vtbl *vtbl; member
169 return buf->vtbl->map(buf, flags, flush_ctx); in pb_map()
180 buf->vtbl->unmap(buf); in pb_unmap()
196 assert(buf->vtbl->get_base_buffer); in pb_get_base_buffer()
197 buf->vtbl->get_base_buffer(buf, base_buf, offset); in pb_get_base_buffer()
209 assert(buf->vtbl->validate); in pb_validate()
210 return buf->vtbl->validate(buf, vl, flags); in pb_validate()
220 assert(buf->vtbl->fence); in pb_fence()
221 buf->vtbl->fence(buf, fence); in pb_fence()
232 buf->vtbl->destroy(buf); in pb_destroy()
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_mode_3_to_9.s205 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
208 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0)
212 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1)
216 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
222 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
226 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2)
233 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3)
237 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
244 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4)
248 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_filters_luma_mode_11_to_17.s315 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0)
318 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0)
322 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1)
326 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
332 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2)
336 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2)
343 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3)
347 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
354 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4)
358 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_chroma_mode_3_to_9.s201 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
204 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0)
210 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1)
214 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1)
220 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
224 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2)
231 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3)
235 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3)
242 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4)
246 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
Dihevc_intra_pred_filters_chroma_mode_11_to_17.s314 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0)
317 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0)
324 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1)
328 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1)
334 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2)
338 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2)
345 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3)
349 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3)
356 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4)
360 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4)
[all …]
/external/capstone/suite/MC/ARM/
Dneon-table-encoding.s.cs2 0xa0,0x08,0xf1,0xf3 = vtbl.8 d16, {d17}, d16
3 0xa2,0x09,0xf0,0xf3 = vtbl.8 d16, {d16, d17}, d18
4 0xa4,0x0a,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18}, d20
5 0xa4,0x0b,0xf0,0xf3 = vtbl.8 d16, {d16, d17, d18, d19}, d20
Dneont2-table-encoding.s.cs2 0xf1,0xff,0xa0,0x08 = vtbl.8 d16, {d17}, d16
3 0xf0,0xff,0xa2,0x09 = vtbl.8 d16, {d16, d17}, d18
4 0xf0,0xff,0xa4,0x0a = vtbl.8 d16, {d16, d17, d18}, d20
5 0xf0,0xff,0xa4,0x0b = vtbl.8 d16, {d16, d17, d18, d19}, d20
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.c106 if (intel->vtbl.debug_batch != NULL) in do_batch_dump()
107 intel->vtbl.debug_batch(intel); in do_batch_dump()
123 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub) in do_flush_locked()
124 intel->vtbl.annotate_aub(intel); in do_flush_locked()
137 intel->vtbl.new_batch(intel); in do_flush_locked()
162 if (intel->vtbl.finish_batch) in _intel_batchbuffer_flush()
163 intel->vtbl.finish_batch(intel); in _intel_batchbuffer_flush()
Di915_vtbl.c804 intel->vtbl.set_draw_region(intel, &colorRegion, depthRegion, in i915_update_draw_buffer()
858 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size; in i915InitVtbl()
859 i915->intel.vtbl.destroy = i915_destroy_context; in i915InitVtbl()
860 i915->intel.vtbl.emit_state = i915_emit_state; in i915InitVtbl()
861 i915->intel.vtbl.new_batch = i915_new_batch; in i915InitVtbl()
862 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state; in i915InitVtbl()
863 i915->intel.vtbl.render_start = i915_render_start; in i915InitVtbl()
864 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate; in i915InitVtbl()
865 i915->intel.vtbl.set_draw_region = i915_set_draw_region; in i915InitVtbl()
866 i915->intel.vtbl.update_draw_buffer = i915_update_draw_buffer; in i915InitVtbl()
[all …]
Di830_vtbl.c832 intel->vtbl.set_draw_region(intel, colorRegions, depthRegion, in i830_update_draw_buffer()
880 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size; in i830InitVtbl()
881 i830->intel.vtbl.destroy = i830_destroy_context; in i830InitVtbl()
882 i830->intel.vtbl.emit_state = i830_emit_state; in i830InitVtbl()
883 i830->intel.vtbl.new_batch = i830_new_batch; in i830InitVtbl()
884 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state; in i830InitVtbl()
885 i830->intel.vtbl.set_draw_region = i830_set_draw_region; in i830InitVtbl()
886 i830->intel.vtbl.update_draw_buffer = i830_update_draw_buffer; in i830InitVtbl()
887 i830->intel.vtbl.update_texture_state = i830UpdateTextureState; in i830InitVtbl()
888 i830->intel.vtbl.render_start = i830_render_start; in i830InitVtbl()
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/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_context.c126 radeon->vtbl.swtcl_flush = r100_swtcl_flush; in r100_init_vtbl()
127 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; in r100_init_vtbl()
128 radeon->vtbl.fallback = radeonFallback; in r100_init_vtbl()
129 radeon->vtbl.free_context = r100_vtbl_free_context; in r100_init_vtbl()
130 radeon->vtbl.emit_query_finish = r100_emit_query_finish; in r100_init_vtbl()
131 radeon->vtbl.check_blit = r100_check_blit; in r100_init_vtbl()
132 radeon->vtbl.blit = r100_blit; in r100_init_vtbl()
133 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; in r100_init_vtbl()
134 radeon->vtbl.revalidate_all_buffers = r100ValidateBuffers; in r100_init_vtbl()
Dradeon_common.c137 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
138 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
214 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
260 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
262 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); in radeon_draw_buffer()
268 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
270 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); in radeon_draw_buffer()
273 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
280 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); in radeon_draw_buffer()
285 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE); in radeon_draw_buffer()
[all …]
Dradeon_tex_copy.c57 if (!radeon->vtbl.blit) { in do_copy_texsubimage()
101 if (!radeon->vtbl.check_blit(dst_mesaformat, rrb->pitch / rrb->cpp)) { in do_copy_texsubimage()
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp, in do_copy_texsubimage()
Dradeon_pixel_read.c109 !radeon->vtbl.check_blit(dst_format, rrb->pitch / rrb->cpp) || !radeon->vtbl.blit) { in do_blit_readpixels()
158 if (radeon->vtbl.blit(ctx, in do_blit_readpixels()
/external/mesa3d/src/gallium/auxiliary/util/
Du_transfer.c120 return ur->vtbl->resource_get_handle(screen, resource, handle); in u_resource_get_handle_vtbl()
127 ur->vtbl->resource_destroy(screen, resource); in u_resource_destroy_vtbl()
138 return ur->vtbl->transfer_map(context, resource, level, usage, box, in u_transfer_map_vtbl()
147 ur->vtbl->transfer_flush_region(pipe, transfer, box); in u_transfer_flush_region_vtbl()
154 ur->vtbl->transfer_unmap(pipe, transfer); in u_transfer_unmap_vtbl()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dradeon_common.c137 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
138 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
214 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
260 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); in radeon_draw_buffer()
262 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); in radeon_draw_buffer()
268 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
270 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); in radeon_draw_buffer()
273 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); in radeon_draw_buffer()
280 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); in radeon_draw_buffer()
285 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE); in radeon_draw_buffer()
[all …]
Dr200_context.c161 radeon->vtbl.swtcl_flush = r200_swtcl_flush; in r200_init_vtbl()
162 radeon->vtbl.fallback = r200Fallback; in r200_init_vtbl()
163 radeon->vtbl.update_scissor = r200_vtbl_update_scissor; in r200_init_vtbl()
164 radeon->vtbl.emit_query_finish = r200_emit_query_finish; in r200_init_vtbl()
165 radeon->vtbl.check_blit = r200_check_blit; in r200_init_vtbl()
166 radeon->vtbl.blit = r200_blit; in r200_init_vtbl()
167 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; in r200_init_vtbl()
168 radeon->vtbl.revalidate_all_buffers = r200ValidateBuffers; in r200_init_vtbl()
Dradeon_tex_copy.c57 if (!radeon->vtbl.blit) { in do_copy_texsubimage()
101 if (!radeon->vtbl.check_blit(dst_mesaformat, rrb->pitch / rrb->cpp)) { in do_copy_texsubimage()
128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp, in do_copy_texsubimage()
Dradeon_pixel_read.c109 !radeon->vtbl.check_blit(dst_format, rrb->pitch / rrb->cpp) || !radeon->vtbl.blit) { in do_blit_readpixels()
158 if (radeon->vtbl.blit(ctx, in do_blit_readpixels()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen8_surface_state.c82 brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; in gen8_init_vtable_surface_functions()
83 brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state; in gen8_init_vtable_surface_functions()
/external/mesa3d/src/egl/drivers/dri2/
Degl_dri2.c1279 return dri2_dpy->vtbl->destroy_surface(drv, dpy, surf); in dri2_destroy_surface()
1312 ddraw = (dsurf) ? dri2_dpy->vtbl->get_dri_drawable(dsurf) : NULL; in dri2_make_current()
1313 rdraw = (rsurf) ? dri2_dpy->vtbl->get_dri_drawable(rsurf) : NULL; in dri2_make_current()
1384 return dri2_dpy->vtbl->create_window_surface(drv, dpy, conf, native_window, in dri2_create_window_surface()
1394 return dri2_dpy->vtbl->create_pixmap_surface(drv, dpy, conf, native_pixmap, in dri2_create_pixmap_surface()
1403 return dri2_dpy->vtbl->create_pbuffer_surface(drv, dpy, conf, attrib_list); in dri2_create_pbuffer_surface()
1411 return dri2_dpy->vtbl->swap_interval(drv, dpy, surf, interval); in dri2_swap_interval()
1422 __DRIdrawable *dri_drawable = dri2_dpy->vtbl->get_dri_drawable(draw); in dri2_flush_drawable_for_swapbuffers()
1454 return dri2_dpy->vtbl->swap_buffers(drv, dpy, surf); in dri2_swap_buffers()
1463 return dri2_dpy->vtbl->swap_buffers_with_damage(drv, dpy, surf, in dri2_swap_buffers_with_damage()
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