| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 959 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
1038 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1137 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local
1348 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
1360 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
1677 unsigned TmpReg = createResultReg(RC); in SelectRet() local
1686 unsigned TmpReg = createResultReg(RC); in SelectRet() local
1918 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCMaterializeFP() local
2020 unsigned TmpReg = createResultReg(RC); in PPCMaterialize32BitInt() local
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| D | PPCFrameLowering.cpp | 1825 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
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| D | PPCISelLowering.cpp | 8469 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local
8553 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
9270 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 518 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
587 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
668 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
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| D | SIFixSGPRCopies.cpp | 227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
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| D | SIInstrInfo.cpp | 727 MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, in calculateLDSSpillAddress()
2681 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
2901 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 289 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
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| D | PPCFrameLowering.cpp | 664 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; in emitEpilogue() local
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| D | PPCISelLowering.cpp | 4678 unsigned TmpReg = (!BinOpcode) ? incr : in EmitAtomicBinary() local
4762 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
5086 unsigned TmpReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 223 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI)); in ExpandFPMLxInstruction() local
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| D | Thumb1RegisterInfo.cpp | 655 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local
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| D | ThumbRegisterInfo.cpp | 570 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
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| D | ARMISelLowering.cpp | 8507 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass in attachMEMCPYScratchRegs() local
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2176 unsigned TmpReg = DstReg; in loadImmediate() local
2204 unsigned TmpReg = DstReg; in loadImmediate() local
2415 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress() local
2516 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress() local
3389 unsigned TmpReg = DReg; in expandRotation() local
3518 unsigned TmpReg = DReg; in expandDRotation() local
4666 unsigned TmpReg = PrevReg + 1; in parseRegisterList() local
5500 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; in parseDirectiveCPSetup() local
6152 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; in ParseDirective() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 590 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
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| D | MipsFastISel.cpp | 333 unsigned TmpReg = createResultReg(RC); in materialize32BitInt() local
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 286 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset()
325 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithSymOffset()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1675 unsigned TmpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1998 unsigned TmpReg = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect() local
2010 unsigned TmpReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
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| D | X86ISelLowering.cpp | 22940 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); in EmitVAARG64WithCustomInserter() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 379 unsigned TmpReg = createResultReg(RC); in materializeFP() local
4002 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSL_ri() local
4123 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitLSR_ri() local
4232 unsigned TmpReg = MRI.createVirtualRegister(RC); in emitASR_ri() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon01f3a6ab0111::X86AsmParser::IntelExprStateMachine
1297 unsigned TmpReg; in ParseIntelExpression() local
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 338 unsigned TmpReg = FromReg; in isRevCopyChain() local
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 11563 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); in EmitVAARG64WithCustomInserter() local
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