| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 717 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 855 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | README.txt | 69 SETOGE unimplemented
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 167 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
191 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 60 defm GE : ComparisonFP<SETOGE, "ge ">;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | Analysis.cpp | 157 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break; in getFCmpCondCode()
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 319 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: in Select()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 549 case ISD::SETOGE: in getPredicateForSetCC()
598 case ISD::SETOGE: in getCRIdxForSetCC()
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| D | PPCISelLowering.cpp | 246 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
247 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
3596 case ISD::SETOGE: in LowerSELECT_CC()
3621 case ISD::SETOGE: in LowerSELECT_CC()
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 175 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 333 case ISD::SETOGE: return "setoge"; in getOperationName()
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| D | TargetLowering.cpp | 174 case ISD::SETOGE: in softenSetCCOperands()
1959 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
1960 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
1962 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2094 case ISD::SETOGE: in getPredicateForSetCC()
2139 case ISD::SETOGE: in getCRIdxForSetCC()
2162 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; in getVCmpInst()
2173 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
2193 case ISD::SETOGE: in getVCmpInst()
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| D | PPCInstrQPX.td | 992 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETOGE),
1039 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETOGE),
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 492 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
774 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 101 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
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| D | AMDGPUISelLowering.cpp | 1011 case ISD::SETOGE: in CombineFMinMaxLegacy()
1307 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24()
1748 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND32()
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 656 case ISD::SETOGE: in EmitCmp()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 592 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
977 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2378 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) in SimplifySetCC()
2379 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
2381 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) in SimplifySetCC()
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| D | LegalizeFloatTypes.cpp | 632 case ISD::SETOGE: in SoftenSetCCOperands()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in MipsSETargetLowering()
196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering()
323 setCondCodeAction(ISD::SETOGE, Ty, Expand); in addMSAFloatType()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 591 defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">;
600 defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">;
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 677 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 841 case ISD::SETOGE: in IntCondCCodeToICC()
|