1/* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17/* 18 Art assembly interpreter notes: 19 20 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 21 handle invoke, allows higher-level code to create frame & shadow frame. 22 23 Once that's working, support direct entry code & eliminate shadow frame (and 24 excess locals allocation. 25 26 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the 27 base of the vreg array within the shadow frame. Access the other fields, 28 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 29 the shadow frame mechanism of double-storing object references - via rFP & 30 number_of_vregs_. 31 32 */ 33 34/* 35ARM EABI general notes: 36 37r0-r3 hold first 4 args to a method; they are not preserved across method calls 38r4-r8 are available for general use 39r9 is given special treatment in some situations, but not for us 40r10 (sl) seems to be generally available 41r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 42r12 (ip) is scratch -- not preserved across method calls 43r13 (sp) should be managed carefully in case a signal arrives 44r14 (lr) must be preserved 45r15 (pc) can be tinkered with directly 46 47r0 holds returns of <= 4 bytes 48r0-r1 hold returns of 8 bytes, low word in r0 49 50Callee must save/restore r4+ (except r12) if it modifies them. If VFP 51is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 52s0-s15 (d0-d7, q0-a3) do not need to be. 53 54Stack is "full descending". Only the arguments that don't fit in the first 4 55registers are placed on the stack. "sp" points at the first stacked argument 56(i.e. the 5th arg). 57 58VFP: single-precision results in s0, double-precision results in d0. 59 60In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 6164-bit quantities (long long, double) must be 64-bit aligned. 62*/ 63 64/* 65Mterp and ARM notes: 66 67The following registers have fixed assignments: 68 69 reg nick purpose 70 r4 rPC interpreted program counter, used for fetching instructions 71 r5 rFP interpreted frame pointer, used for accessing locals and args 72 r6 rSELF self (Thread) pointer 73 r7 rINST first 16-bit code unit of current instruction 74 r8 rIBASE interpreted instruction base pointer, used for computed goto 75 r10 rPROFILE branch profiling countdown 76 r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 77 78Macros are provided for common operations. Each macro MUST emit only 79one instruction to make instruction-counting easier. They MUST NOT alter 80unspecified registers or condition codes. 81*/ 82 83/* 84 * This is a #include, not a %include, because we want the C pre-processor 85 * to expand the macros into assembler assignment statements. 86 */ 87#include "asm_support.h" 88#include "interpreter/cfi_asm_support.h" 89 90#define MTERP_PROFILE_BRANCHES 1 91#define MTERP_LOGGING 0 92 93/* During bringup, we'll use the shadow frame model instead of rFP */ 94/* single-purpose registers, given names for clarity */ 95#define rPC r4 96#define CFI_DEX 4 // DWARF register number of the register holding dex-pc (xPC). 97#define CFI_TMP 0 // DWARF register number of the first argument register (r0). 98#define rFP r5 99#define rSELF r6 100#define rINST r7 101#define rIBASE r8 102#define rPROFILE r10 103#define rREFS r11 104 105/* 106 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 107 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 108 */ 109#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 110#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 111#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 112#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 113#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 114#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 115#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 116#define OFF_FP_DEX_INSTRUCTIONS OFF_FP(SHADOWFRAME_DEX_INSTRUCTIONS_OFFSET) 117#define OFF_FP_SHADOWFRAME OFF_FP(0) 118 119/* 120 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 121 * be done *before* something throws. 122 * 123 * It's okay to do this more than once. 124 * 125 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 126 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 127 * offset into the code_items_[] array. For effiency, we will "export" the 128 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 129 * to convert to a dex pc when needed. 130 */ 131.macro EXPORT_PC 132 str rPC, [rFP, #OFF_FP_DEX_PC_PTR] 133.endm 134 135.macro EXPORT_DEX_PC tmp 136 ldr \tmp, [rFP, #OFF_FP_DEX_INSTRUCTIONS] 137 str rPC, [rFP, #OFF_FP_DEX_PC_PTR] 138 sub \tmp, rPC, \tmp 139 asr \tmp, #1 140 str \tmp, [rFP, #OFF_FP_DEX_PC] 141.endm 142 143/* 144 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 145 */ 146.macro FETCH_INST 147 ldrh rINST, [rPC] 148.endm 149 150/* 151 * Fetch the next instruction from the specified offset. Advances rPC 152 * to point to the next instruction. "_count" is in 16-bit code units. 153 * 154 * Because of the limited size of immediate constants on ARM, this is only 155 * suitable for small forward movements (i.e. don't try to implement "goto" 156 * with this). 157 * 158 * This must come AFTER anything that can throw an exception, or the 159 * exception catch may miss. (This also implies that it must come after 160 * EXPORT_PC.) 161 */ 162.macro FETCH_ADVANCE_INST count 163 ldrh rINST, [rPC, #((\count)*2)]! 164.endm 165 166/* 167 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 168 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 169 */ 170.macro PREFETCH_ADVANCE_INST dreg, sreg, count 171 ldrh \dreg, [\sreg, #((\count)*2)]! 172.endm 173 174/* 175 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 176 * rINST ahead of possible exception point. Be sure to manually advance rPC 177 * later. 178 */ 179.macro PREFETCH_INST count 180 ldrh rINST, [rPC, #((\count)*2)] 181.endm 182 183/* Advance rPC by some number of code units. */ 184.macro ADVANCE count 185 add rPC, #((\count)*2) 186.endm 187 188/* 189 * Fetch the next instruction from an offset specified by _reg. Updates 190 * rPC to point to the next instruction. "_reg" must specify the distance 191 * in bytes, *not* 16-bit code units, and may be a signed value. 192 * 193 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 194 * bits that hold the shift distance are used for the half/byte/sign flags. 195 * In some cases we can pre-double _reg for free, so we require a byte offset 196 * here. 197 */ 198.macro FETCH_ADVANCE_INST_RB reg 199 ldrh rINST, [rPC, \reg]! 200.endm 201 202/* 203 * Fetch a half-word code unit from an offset past the current PC. The 204 * "_count" value is in 16-bit code units. Does not advance rPC. 205 * 206 * The "_S" variant works the same but treats the value as signed. 207 */ 208.macro FETCH reg, count 209 ldrh \reg, [rPC, #((\count)*2)] 210.endm 211 212.macro FETCH_S reg, count 213 ldrsh \reg, [rPC, #((\count)*2)] 214.endm 215 216/* 217 * Fetch one byte from an offset past the current PC. Pass in the same 218 * "_count" as you would for FETCH, and an additional 0/1 indicating which 219 * byte of the halfword you want (lo/hi). 220 */ 221.macro FETCH_B reg, count, byte 222 ldrb \reg, [rPC, #((\count)*2+(\byte))] 223.endm 224 225/* 226 * Put the instruction's opcode field into the specified register. 227 */ 228.macro GET_INST_OPCODE reg 229 and \reg, rINST, #255 230.endm 231 232/* 233 * Put the prefetched instruction's opcode field into the specified register. 234 */ 235.macro GET_PREFETCHED_OPCODE oreg, ireg 236 and \oreg, \ireg, #255 237.endm 238 239/* 240 * Begin executing the opcode in _reg. Because this only jumps within the 241 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 242 */ 243.macro GOTO_OPCODE reg 244 add pc, rIBASE, \reg, lsl #${handler_size_bits} 245.endm 246.macro GOTO_OPCODE_BASE base,reg 247 add pc, \base, \reg, lsl #${handler_size_bits} 248.endm 249 250/* 251 * Get/set the 32-bit value from a Dalvik register. 252 */ 253.macro GET_VREG reg, vreg 254 ldr \reg, [rFP, \vreg, lsl #2] 255.endm 256.macro SET_VREG reg, vreg 257 str \reg, [rFP, \vreg, lsl #2] 258 mov \reg, #0 259 str \reg, [rREFS, \vreg, lsl #2] 260.endm 261.macro SET_VREG_OBJECT reg, vreg, tmpreg 262 str \reg, [rFP, \vreg, lsl #2] 263 str \reg, [rREFS, \vreg, lsl #2] 264.endm 265.macro SET_VREG_SHADOW reg, vreg 266 str \reg, [rREFS, \vreg, lsl #2] 267.endm 268 269/* 270 * Clear the corresponding shadow regs for a vreg pair 271 */ 272.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 273 mov \tmp1, #0 274 add \tmp2, \vreg, #1 275 SET_VREG_SHADOW \tmp1, \vreg 276 SET_VREG_SHADOW \tmp1, \tmp2 277.endm 278 279/* 280 * Convert a virtual register index into an address. 281 */ 282.macro VREG_INDEX_TO_ADDR reg, vreg 283 add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ 284.endm 285 286/* 287 * Refresh handler table. 288 */ 289.macro REFRESH_IBASE 290 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 291.endm 292 293/* 294 * cfi support macros. 295 */ 296.macro ENTRY name 297 .arm 298 .type \name, #function 299 .hidden \name // Hide this as a global symbol, so we do not incur plt calls. 300 .global \name 301 /* Cache alignment for function entry */ 302 .balign 16 303\name: 304 .cfi_startproc 305 .fnstart 306.endm 307 308.macro END name 309 .fnend 310 .cfi_endproc 311 .size \name, .-\name 312.endm 313